Texas-instruments TMS320C64x DSP Manual do Utilizador descarregar pdf (Página 27)

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101

Video Port FIFO

Overview1-10 SPRU629

For 8/10-bit raw video, the FIFO is configured as a single buffer as shown in

Figure 1–7. The FIFO outputs data on the VDOUT[9–0] half of the bus. The

FIFO has a single read pointer and write register (YDSTA).

Figure 1–7. 8/10-Bit Raw Video Display FIFO Configuration

Data Buffer

(5120 bytes)

YDSTA

VDOUT[9–0]

8/10

Display FIFO

For locked raw video, the FIFO is split into channel A and B. The channels are

locked together and use the same clock and control signals. Each channel

uses a single buffer and write register (YDSTx) as shown in Figure 1–8.

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