Texas Instruments MSP50C614 Manual do Utilizador

MSP50C614Mixed-Signal ProcessorUser’s GuideSPSU014January 2000Printed on Recycled Paper

Contentsx 5.9.10 String Functions 5-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9.11 C

Instruction Syntax and Addressing Modes 4-84.3 Instruction Syntax and Addressing ModesMSP50P614/MSP50C614 instructions can perform multiple operations

Instruction Syntax and Addressing Modes4-9Assembly Language Instructions4.3.2 Addressing ModesThe addressing modes on the MSP50P614/MSP50C614 are imme

Instruction Syntax and Addressing Modes 4-10Table 4–3. Rx Bit DescriptionRxOperation0 0 0 R00 0 1 R10 1 0 R20 1 1 R31 0 0 R4 or LOOP1 0 1 R5 or INDEX1

Instruction Syntax and Addressing Modes4-11Assembly Language InstructionsTable 4–5. MSP50P614/MSP50C614 Addressing Modes SummaryADDRESSING SYNTAX OPER

Instruction Syntax and Addressing Modes 4-12For any particular addressing mode, replace the {adrs} with the syntax shownin Table 4–4. To encode the i

Instruction Syntax and Addressing Modes4-13Assembly Language Instructions4.3.3 Immediate AddressingThe address of the memory location is encoded in th

Instruction Syntax and Addressing Modes 4-144.3.4 Direct AddressingDirect addressing always requires two instruction words. The second wordoperand is

Instruction Syntax and Addressing Modes4-15Assembly Language Instructions4.3.5 Indirect AddressingIndirect addressing uses one of 8 registers (R0...R7

Instruction Syntax and Addressing Modes 4-16Example 4.3.12 MOV *R5++R5, A0~, ++ARefer to the initial processor state in Table 4–8 before execution of

Instruction Syntax and Addressing Modes4-17Assembly Language InstructionsAddress+Rx(x = 0 – 7)Index Register (R5)OperandExample 4.3.17 AND A0, *R3+R5R

ContentsxiContentsB.3.5 Host Write Sequence B-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3.6 H

Instruction Syntax and Addressing Modes 4-18Example 4.3.20 MOV A3, *R6+0x10Refer to the initial processor state in Table 4–8 before execution of this

Instruction Syntax and Addressing Modes4-19Assembly Language Instructions4.3.7 Flag AddressingThis addressing mode addresses only the 17th bit (the fl

Instruction Syntax and Addressing Modes 4-204.3.8 Tag/Flag BitsThe words TAG and flag may be used interchangeably in this manual. TheTAG bit is the 17

Instruction Syntax and Addressing Modes4-21Assembly Language InstructionsHowever, xFLAG instructions use {flagadrs} addressing modes. This includesglo

Instruction Classification 4-224.4 Instruction ClassificationThe machine level instruction set is divided into a number of classes. Theclasses are pri

Instruction Classification4-23Assembly Language InstructionsTable 4–11. Symbols and Explanation (Continued)Symbol Explanationnext A Accumulator contro

Instruction Classification 4-24Table 4–11. Instruction Classification (Continued)Class Sub-ClassDescription4 Register and memory referenceA Memory ref

Instruction Classification4-25Assembly Language InstructionsTable 4–12. Classes and Opcode DefinitionBit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Class

Instruction Classification 4-26Class 1a provides the four basic instructions of load, store, add, and subtractbetween accumulator and data memory. Eit

Instruction Classification4-27Assembly Language InstructionsTable 4–15. Class 1b Instruction DescriptionC1b Mnemonic Description0 0 0 0 OR An, {adrs}O

Figuresxii Figures1–1 Functional Block Diagram for the C614 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Instruction Classification 4-28Table 4–15. Class 1b Instruction Description (Continued)C1b Mnemonic Description1 0 1 1 MULAPL An, {adrs}MULAPLS An, {a

Instruction Classification4-29Assembly Language Instructionsconstants. Long constants (16 bits) and long string constants differ in that ref-erences a

Instruction Classification 4-30Table 4–18. Class 2b Instruction DescriptionC2b Mnemonic Description0 0 0 ADD An[~], An[~], imm16 [, next A]ADDS An[~],

Instruction Classification4-31Assembly Language Instructionsbetween the accumulator and the MR, SV, or PH register. As with all accumula-tor reference

Instruction Classification 4-32Table 4–20. Class 3 Instruction Description (Continued)C3 Mnemonic Description0 1 0 0 0 XOR An[~], An~, An [, next A]XO

Instruction Classification4-33Assembly Language InstructionsTable 4–20. Class 3 Instruction Description (Continued)C3 Mnemonic Description1 0 1 0 0 MO

Instruction Classification 4-34Table 4–20. Class 3 Instruction Description (Continued)C3 Mnemonic Description1 1 1 1 0 MUL An[~] [, next A]MULS An[~]M

Instruction Classification4-35Assembly Language InstructionsTable 4–22. Class 4a Instruction DescriptionC4a Mnemonic Description0 MOV {adrs}, RxStore

Instruction Classification 4-364.4.5 Class 5 Instructions: Memory ReferenceClass 5 instructions provide transfer to and from data memory and all regis

Instruction Classification4-37Assembly Language InstructionsTable 4–27. Class 5 Instruction Description (Continued)C5 Mnemonic Description0 1 0 1 1 MO

FiguresxiiiContents5–9 Select Program Folder Dialog 5-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Instruction Classification 4-38Table 4–27. Class 5 Instruction Description (Continued)C5 Mnemonic Description1 1 1 1 0 RPT {adrs}8Load repeat counter

Instruction Classification4-39Assembly Language InstructionsTable 4–30. Class 6b Instruction DescriptionC6b Mnemonic Description0 IN An[~], port6INS A

Instruction Classification 4-40Table 4–31. Class 7 Instruction Encoding and DescriptionBit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0VCALLvector81 1 1 1

Instruction Classification4-41Assembly Language InstructionsTable 4–31. Class 7 Instruction Encoding and Description (Continued)cccc namesDescriptionc

Instruction Classification 4-42Table 4–33. Class 8a Instruction DescriptionC8a Mnemonic Description0 0 0 MOV TFn, {flagadrs} Load flag bit (17th bit)

Instruction Classification4-43Assembly Language InstructionsTable 4–35. Class 9a Instruction EncodingBit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Class

Bit, Byte, Word and String Addressing 4-44Table 4–38. Class 9c Instruction DescriptionC9c Mnemonic Description0 MOV APn, imm6Load the accumulator poin

Bit, Byte, Word and String Addressing4-45Assembly Language Instructionsis a string of bytes. The length of the byte string is stored in the string reg

Bit, Byte, Word and String Addressing 4-46Flag address: The flag (or TAG) address uses linear addressing from 0 to thesize of data memory in 17 bit wi

Bit, Byte, Word and String Addressing4-47Assembly Language InstructionsFigure 4–4. Data Memory ExampleAbsolute WordMemory LocationData Memory Location

Tablesxiv Tables1–1 Signal and Pad Descriptions for the C614 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 MSP

Bit, Byte, Word and String Addressing 4-48Example 4.5.7 MOV STR, 4–2MOV AP0, 2MOV R0, 0x0001 * 2MOVBS A0, *R0++Refer to Figure 4–4 for this example. T

MSP50P614/MSP50C614 Computational Modes4-49Assembly Language InstructionsExample 4.5.10 MOV STR, 0SFLAG *0x00032MOVS A0, *0x0031 * 2RFLAG *0x00032MOVS

MSP50P614/MSP50C614 Computational Modes 4-50Table 4–41. MSP50P614/MSP50C614 Computational ModesComputationalModeSettingInstructionResettingInstruction

MSP50P614/MSP50C614 Computational Modes4-51Assembly Language InstructionsExample 4.6.2 SXMMOV STR, 2–2 ; string length=2MOV MR, 0x8000MOV A0, 0x800

MSP50P614/MSP50C614 Computational Modes 4-52Example 4.6.1 SOVMMOV A0, 0x7FFEADD A0, 5In this example, we set the overflow mode (OM = 1 of STAT). Addin

Hardware Loop Instructions4-53Assembly Language Instructionshigh word of the result is stored in the PH register and is 0x3FFF. The low wordis stored

Hardware Loop Instructions 4-54the execution of a string instruction, interrupts are queued. Queued interruptsare serviced according to their priority

String Instructions4-55Assembly Language Instructions4.8 String InstructionsClass 1, 2, 3, and 6 instructions can have string modes. During the execut

String Instructions 4-56A1 string is 0x233EFBCA1223 and *0x200 = 0x9086EE3412AC. STR =3–2=1, defines a string length of 3. Final result, A1~ string =0

Lookup Instructions4-57Assembly Language Instructions4.9 Lookup InstructionsTable lookup instructions transfer data from program memory (ROM) to datam

TablesxvContents4–25 Class 4d Instruction Description 4-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lookup Instructions 4-58Lookup instructions make use of the data pointer (DP) internally. The DPstores the address of the program memory location, loa

Input/Output Instructions4-59Assembly Language Instructions4.10 Input/Output InstructionsThe MSP50P614/MSP50C614 processor communicates with other on-

Special Filter Instructions 4-60N tap filters ideally require 2N multiply–accumulates. Four instructions areprovided to compute this equation: FIR, FI

Special Filter Instructions4-61Assembly Language Instructionstheory requires). The second to last RAM location in the circular buffer istagged using a

Special Filter Instructions 4-62After the FIR or COR instruction executes, the new startOfBuff will be thelast location in the circular buffer. After

Special Filter Instructions4-63Assembly Language Instructionsmov A0,*nextSample ;Replace last sample with newest samplemov *R0,A0 ; and update the s

Special Filter Instructions 4-64Any combination of registers different from the above will yield incorrectresults with the FIR/COR instruction.Use R5

Special Filter Instructions4-65Assembly Language InstructionsImportant note about setting the STAT registerIt is very important to consider the initia

Special Filter Instructions 4-66mov STAT,*filterSTAT_tag ;load STAT with last filter tag statusrpt N–2firk A0,*R0++ ;Do one sample ––> 32 bit resul

Special Filter Instructions4-67Assembly Language InstructionsFigure 4–6. Setup and Execution of MSP50P614/MSP50C614 Filter Instructions,N+1 TapsAccumu

Notes, Cautions, and Warningsxvi Notes, Cautions, and WarningsMSP50C605 and MSP50C604 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Special Filter Instructions 4-68Figure 4–7. Filter Instruction and Circular Buffering for N+1 Tap Filter16 BitsTAGAC n+1AC n+2 AC nyif TAG = 1Rxevenco

Conditionals4-69Assembly Language Instructions4.12 ConditionalsThe condition bits in the status register (STAT) are used to modify programcontrol thro

Legend 4-704.13 LegendAll instructions of the MSP50P614/MSP50C614 use the following syntax:name [dest] [, src] [, src1] [, mod]nameName of the instruc

Legend4-71Assembly Language InstructionsSymbol MeaningA~ Select offset accumulator as the source if this bit is 1. Used in opcode encoding only.~A Sel

Legend 4-72Symbol MeaningnRValue in repeat counter loaded by RPT instructionsnsValue in string register STROF Overflow flagoffset[n]n bit offset from

Legend4-73Assembly Language InstructionsTable 4–45. Auto Increment and DecrementOperationnext Ab9 b8No modification 0 0Auto increment ++A 0 1Auto Decr

Individual Instruction Descriptions 4-744.14 Individual Instruction DescriptionsIn this section, individual instructions are discussed in detail. Use

Individual Instruction Descriptions4-75Assembly Language Instructions4.14.1 ADD Add wordSyntax[label] namedest, src [, src1] [,mod] Clock, clkWords, w

Individual Instruction Descriptions 4-76DescriptionSyntax DescriptionADD dest, srcADD src with dest and store the result to dest.ADD dest, src, src1 [

Individual Instruction Descriptions4-77Assembly Language Instructions4.14.2 ADDB ADD BYTESyntax[label]name dest, srcClock, clkWords, wWith RPT, clkCla

1-1Introduction to the MSP50C614The MSP50C614 (C614) is a low cost, mixed signal controller, that combinesa speech synthesizer, general-purpose I/O, o

Individual Instruction Descriptions 4-784.14.3 ADDS Add StringSyntax[label]name dest, src, src1Clock, clkWords, wWith RPT, clkClassADDS An[~], An, {ad

Individual Instruction Descriptions4-79Assembly Language InstructionsExample 4.14.3.3 ADDS A1, A1~, A1Add accumulator string A1 to accumulator string

Individual Instruction Descriptions 4-804.14.4 AND Bitwise ANDSyntax[label] name dest, src [, src1] [, mod] Clock, clkWord, wWith RPT, clkClassAND An,

Individual Instruction Descriptions4-81Assembly Language InstructionsSee Also ANDS, ANDB, OR, ORB, ORS, XOR, XORB, XORSExample 4.14.4.1 AND A3, *R4—–A

Individual Instruction Descriptions 4-824.14.5 ANDB Bitwise AND ByteSyntax[label] name dest, srcClock, clkWord, wWith RPT, clkClassANDB An, imm81 1 N/

Individual Instruction Descriptions4-83Assembly Language Instructions4.14.6 ANDS Bitwise AND StringSyntax[label] name dest, src [, src1] Clock, clkWor

Individual Instruction Descriptions 4-844.14.7 BEGLOOP Begin LoopSyntax[label] nameClock, clkWord, wWith RPT, clkClassBEGLOOP†1 1 N/R 9d†Loop must end

Individual Instruction Descriptions4-85Assembly Language Instructions4.14.8 CALL Unconditional Subroutine CallSyntax[label] name addressClock, clkWord

Individual Instruction Descriptions 4-864.14.9 CccConditional Subroutine CallSyntax[label] name addressClock, clkWord, wWith RPT, clkClassCcc†pma162 2

Individual Instruction Descriptions4-87Assembly Language InstructionsTable 4–48. Names for cccccc namesDescriptioncccc nameNot cc namepTrue condition

Features of the C614 1-21.1 Features of the C614Advanced, integrated speech synthesizer for high quality soundOperates up to 8 MHz (performs up to 8 M

Individual Instruction Descriptions 4-88Description If cc condition in Table 4–48 is true, PC + 2 is pushed onto the stack and thesecond word operand

Individual Instruction Descriptions4-89Assembly Language InstructionsSyntax DescriptionAlternate SyntaxCRC pma16CRNC pma16Conditional call on RCF = 1C

Individual Instruction Descriptions 4-904.14.10 CMP Compare Two Words[label] name src, src1 [, mod] Clock, clkWord, wWith RPT, clkClassCMP An, {adrs}

Individual Instruction Descriptions4-91Assembly Language InstructionsExample 4.14.10.3 CMP R2, 0xfe20Compare value at R2 to immediate value 0xfe20 and

Individual Instruction Descriptions 4-924.14.11 CMPB Compare Two BytesSyntax[label] name src, src1Clock, clkWord, wWith RPT, clkClassCMPB An, imm81 1

Individual Instruction Descriptions4-93Assembly Language Instructions4.14.12 CMPS Compare Two StringsSyntax[label]name src, src1Clock, clkWord, wWith

Individual Instruction Descriptions 4-944.14.13 COR Correlation Filter FunctionSyntax[label]name dest, srcClock, clkWord, wWith RPT, clkClassCOR An, *

Individual Instruction Descriptions4-95Assembly Language Instructions4.14.14 CORK Correlation Filter FunctionSyntax[label] name dest, srcClock, clkWor

Individual Instruction Descriptions 4-964.14.15 ENDLOOP End LoopSyntax[label] name #Clock, clkWord, wWith RPT, clkClassENDLOOP [n] 1 1 N/R 9dExecution

Individual Instruction Descriptions4-97Assembly Language Instructions4.14.16 EXTSGN Sign Extend WordSyntax[label] name dest [, mod] Clock, clkWord, wW

Applications1-3Introduction to the MSP50C6141.2 ApplicationsDue to its low cost, low-power needs, and high programmability, the C614 issuitable for a

Individual Instruction Descriptions 4-984.14.17 EXTSGNS Sign Extend StringSyntax[label] name destClock, clkWord, wWith RPT, clkClassEXTSGNS An[~] nR+3

Individual Instruction Descriptions4-99Assembly Language InstructionsMOV AP1, 3 ; Point to loc corresponding to; extended word in accMOVS A0, *R0 ; R0

Individual Instruction Descriptions 4-1004.14.18 FIR FIR Filter Function (Coefficients in RAM)Syntax[label] name dest, srcClock, clkWord, wWith RPT, c

Individual Instruction Descriptions4-101Assembly Language InstructionsSee Also RPT, FIRK, COR, CORKExample 4.14.18.1 RPT 0FIR A0, *R0Computes the calc

Individual Instruction Descriptions 4-1024.14.19 FIRK FIR Filter Function (Coefficients in ROM)Syntax[label] name dest, srcClock, clkWord, wWith RPT,

Individual Instruction Descriptions4-103Assembly Language Instructions4.14.20 IDLE Halt ProcessorSyntax[label] nameClock, clkWord, wWith RPT, clkClass

Individual Instruction Descriptions 4-1044.14.21 IN Input From Port Into WordSyntax[label] name dest, src1Clock, clkWord, wWith RPT, clkClassIN {adrs}

Individual Instruction Descriptions4-105Assembly Language Instructions4.14.22 INS Input From Port Into StringSyntax[label] name src, src1Clock, clkWor

Individual Instruction Descriptions 4-1064.14.23 INTD Interrupt DisableSyntax[label] nameClock, clkWord, wWith RPT, clkClassINTD 1 1 N/R 9dExecution S

Individual Instruction Descriptions4-107Assembly Language Instructions4.14.24 INTE Interrupt EnableSyntax[label] nameClock, clkWord, wWith RPT, clkCla

IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or servic

Development Device: MSP50P614 1-41.3 Development Device: MSP50P614The MSP50P614 is an EPROM based version of the MSP50C614, and isavailable in 120 pin

Individual Instruction Descriptions 4-1084.14.25 IRET Return From InterruptSyntax[label] nameClock, clkWord, wWith RPT, clkClassIRET 2 1 N/R 5Executio

Individual Instruction Descriptions4-109Assembly Language Instructions4.14.26 JccConditional JumpsSyntax[label] name pma16 [, Rmod] Clock, clkWord, wW

Individual Instruction Descriptions 4-110OpcodeInstructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Jcc pma161 0 0 0 0 0Not cc0 0 0 0 0xpma16Jcc pma

Individual Instruction Descriptions4-111Assembly Language Instructionscc namesDescriptioncccc name Not cc nameDescriptionTrue condition (Not true cond

Individual Instruction Descriptions 4-112Syntax DescriptionAlternateInstructionJRNLZP pma16 [, Rmod] Conditional jump on Rx ≥ 0 after post-modJRZP pma

Individual Instruction Descriptions4-113Assembly Language Instructions4.14.27 JMP Unconditional JumpSyntax[label] name dest [, mod] Clock, clkWord, wW

Individual Instruction Descriptions 4-1144.14.28 MOV Move Data Word From Source to DestinationSyntax[label] name dest, src, [, next A] Clock, clkWord,

Individual Instruction Descriptions4-115Assembly Language Instructions[label]ClassWith RPT, clkWord, wClock, clkdest, src, [, next A]nameMOV TFn, {cc}

Individual Instruction Descriptions 4-116Instructions 012345678910111213141516MOV Rx, R5 1 1 1 1 1 1 1 0 0 1 1 0 Rx0 0MOV SV, imm41 1 1 1 1 1 0 1 0

Individual Instruction Descriptions4-117Assembly Language InstructionsDescription Copy value of src to dest. Premodification of accumulator pointers i

Functional Description1-5Introduction to the MSP50C6141.4 Functional DescriptionThe device consists of a micro-DSP core, embedded program and datamemo

Individual Instruction Descriptions 4-118Syntax DescriptionMOV STR, imm8Move immediate byte to String Register (STR)MOV APn, imm5Move immediate 5-bit

Individual Instruction Descriptions4-119Assembly Language InstructionsExample 4.14.28.13 MOV R1, 0x0200 * 2Load immediate word memory address 0x0200 t

Individual Instruction Descriptions 4-1204.14.29 MOVAPH Move With Adding PHSyntax[label] name dest, src, src1Clock, clkWord, wWith RPT, clkClassMOVAPH

Individual Instruction Descriptions4-121Assembly Language Instructions4.14.30 MOVAPHS Move With Adding PHSyntax[label] name dest, src, src1Clock, clkW

Individual Instruction Descriptions 4-1224.14.31 MOVB Move Byte From Source to DestinationSyntax[label] name dest, srcClock, clkWord, wWith RPT, clkCl

Individual Instruction Descriptions4-123Assembly Language InstructionsExample 4.14.29.2 MOVB *R2, A0Copy lower 8 bits of accumulator A0 to the data me

Individual Instruction Descriptions 4-1244.14.32 MOVBS Move Byte String from Source to DestinationSyntax[label] name dest, srcClock, clkWord, wWith RP

Individual Instruction Descriptions4-125Assembly Language Instructions4.14.33 MOVS Move String from Source to DestinationSyntax[label] name dest, srcC

Individual Instruction Descriptions 4-126Description Copy value of src string to dest string. Premodification of accumulator pointersis allowed with s

Individual Instruction Descriptions4-127Assembly Language Instructions4.14.34 MOVSPH Move With Subtract from PHSyntax[label] name dest, src, src1Clock

C605 and C604 (Preliminary Information) 1-6built in pulse-density-modulated DAC (digital-to-analog converter) with directspeaker-drive capability. The

Individual Instruction Descriptions 4-1284.14.35 MOVSPHS Move String With Subtract From PHSyntax[label] name dest, src, src1Clock, clkWord, wWith RPT,

Individual Instruction Descriptions4-129Assembly Language Instructions4.14.36 MOVT Move Tag From Source to DestinationSyntax[label] name dest, srcCloc

Individual Instruction Descriptions 4-1304.14.37 MOVU Move Data UnsignedSyntax[label] name dest, src [, mod] Clock, clkWord, wWith RPT, clkClassMOVU

Individual Instruction Descriptions4-131Assembly Language InstructionsFigure 4–8. Valid Moves/Transfer in MSP50P614/MSP50C614 Instruction SetPHAnRxAPn

Individual Instruction Descriptions 4-1324.14.38 MUL Multiply (Rounded)Syntax[label] name src [, mod] Clock, clkWord, wWith RPT, clkClassMUL An[~] [,

Individual Instruction Descriptions4-133Assembly Language Instructions4.14.39 MULS Multiply String With No Data TransferSyntax[label] name srcClock, c

Individual Instruction Descriptions 4-1344.14.40 MULAPL Multiply and Accumulate ResultSyntax[label] name dest, src [, mod] Clock, clkWord, wWith RPT,

Individual Instruction Descriptions4-135Assembly Language Instructions4.14.41 MULAPLS Multiply String and Accumulate ResultSyntax[label] name dest, sr

Individual Instruction Descriptions 4-1364.14.42 MULSPL Multiply and Subtract PL From AccumulatorSyntax[label] name dest, src [, mod] Clock, clkWord,

Individual Instruction Descriptions4-137Assembly Language Instructions4.14.43 MULSPLS Multiply String and Subtract PL From AccumulatorSyntax[label] na

C605 and C604 (Preliminary Information)1-7Introduction to the MSP50C614Figure 1–1. Functional Block Diagram for the C614 SCANINSYNCPLLOSCOUTOSCINRESET

Individual Instruction Descriptions 4-1384.14.44 MULTPL Multiply and Transfer PL to AccumulatorSyntax[label] name dest, src [, mod] Clock, clkWord, wW

Individual Instruction Descriptions4-139Assembly Language Instructions4.14.45 MULTPLS Multiply String and Transfer PL to AcumulatorSyntax[label] name

Individual Instruction Descriptions 4-1404.14.46 NEGAC Two’s Complement Negation of AccumulatorSyntax[label] name dest, src [,mod]Clock, clkWord, wWit

Individual Instruction Descriptions4-141Assembly Language Instructions4.14.47 NEGACS Two’s Complement Negation of Accumulator StringSyntax[label] name

Individual Instruction Descriptions 4-1424.14.48 NOP No OperationSyntax[label] nameClock, clkWord, wWith RPT, clkClassNOP 1 1 nR+3 9dExecution PC ⇐ PC

Individual Instruction Descriptions4-143Assembly Language Instructions4.14.49 NOTAC One’s Complement Negation of AccumulatorSyntax[label] name dest, s

Individual Instruction Descriptions 4-1444.14.50 NOTACS One’s Complement Negation of Accumulator StringSyntax[label] name dest, srcClock, clkWord, wWi

Individual Instruction Descriptions4-145Assembly Language Instructions4.14.51 OR Bitwise Logical ORSyntax[label] name dest, src [, src1] [, mod]Clock,

Individual Instruction Descriptions 4-146See Also ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, NOTACSExample 4.14.51.1 OR A0, *R0++R5OR accumulator A0 with

Individual Instruction Descriptions4-147Assembly Language Instructions4.14.52 ORB Bitwise OR ByteSyntax[label] name dest, srcClock, clkWord, wWith RPT

C605 and C604 (Preliminary Information) 1-8Figure 1–2. Oscillator and PLL ConnectionMSP50P614MSP50C614OSCINOSCOUT PLLC(PLL) = 3300 pF†22 pF†22 pF†10 M

Individual Instruction Descriptions 4-1484.14.53 ORS Bitwise OR StringSyntax[label] name dest, src [, src1] Clock, clkWord, wWith RPT, clkClassORS An,

Individual Instruction Descriptions4-149Assembly Language Instructions4.14.54 OUT Output to PortSyntax[label] name dest, srcClock, clkWord, wWith RPT,

Individual Instruction Descriptions 4-1504.14.55 OUTS Output String to PortSyntax[label] name dest, srcClock, clkWord, wWith RPT, clkClassOUTSport6, A

Individual Instruction Descriptions4-151Assembly Language Instructions4.14.56 RET Return From Subroutine (CALL, Ccc)Syntax[label] nameClock, clkWord,

Individual Instruction Descriptions 4-1524.14.57 RFLAG Reset Memory FlagSyntax[label] name srcClock, clkWord, wWith RPT, clkClassRFLAG {flagadrs} 1 1

Individual Instruction Descriptions4-153Assembly Language Instructions4.14.58 RFM Reset Fractional ModeSyntax[label] nameClock, clkWord, wWith RPT, cl

Individual Instruction Descriptions 4-1544.14.59 ROVM Reset Overflow ModeSyntax[label] nameClock, clkWord, wWith RPT, clkClassROVM 1 1 N/R 9dExecution

Individual Instruction Descriptions4-155Assembly Language Instructions4.14.60 RPT Repeat Next InstructionSyntax[label] name srcClock, clkWord, wWith R

Individual Instruction Descriptions 4-1564.14.61 RTAG Reset TagSyntax[label] name destClock, clkWord, wWith RPT, clkClassRTAG {adrs} Table 4–46 Table

Individual Instruction Descriptions4-157Assembly Language Instructions4.14.62 RXM Reset Extended Sign ModeSyntax[label] nameClock, clkWord, wWith RPT,

C605 and C604 (Preliminary Information)1-9Introduction to the MSP50C614Figure 1–3. RESET CircuitResetSwitch1 µF(20%)Inside theMSP50P614MSP50C614VDDVSS

Individual Instruction Descriptions 4-1584.14.63 SFLAG Set Memory FlagSyntax[label] name destClock, clkWord, wWith RPT, clkClassSFLAG {flagadrs} 1 1 N

Individual Instruction Descriptions4-159Assembly Language Instructions4.14.64 SFM Set Fractional ModeSyntax[label] nameClock, clkWord, wWith RPT, clkC

Individual Instruction Descriptions 4-1604.14.65 SHL Shift LeftSyntax[label] name dest [, mod]Clock, clkWord, wWith RPT, clkClassSHL An[~] [, next A]

Individual Instruction Descriptions4-161Assembly Language Instructions4.14.66 SHLAC Shift Left AccumulatorSyntax[label] name dest, src [, mod] Clock,

Individual Instruction Descriptions 4-1624.14.67 SHLACS Shift Left Accumulator String IndividuallySyntax[label] name dest, srcClock, clkWord, wWith RP

Individual Instruction Descriptions4-163Assembly Language Instructions4.14.68 SHLAPL Shift Left with AccumulateSyntax[label] name dest, src [, mod] Cl

Individual Instruction Descriptions 4-1644.14.69 SHLAPLS Shift Left String With AccumulateSyntax[label] name dest, srcClock, clkWord, wWith RPT, clkCl

Individual Instruction Descriptions4-165Assembly Language Instructions4.14.70 SHLS Shift Left Accumulator String to ProductSyntax[label] name destCloc

Individual Instruction Descriptions 4-1664.14.71 SHLSPL Shift Left With Subtract PLSyntax[label] name dest, src [, mod] Clock, clkWord, wWith RPT, clk

Individual Instruction Descriptions4-167Assembly Language Instructions4.14.72 SHLSPLS Shift Left String With Subtract PLSyntax[label] name dest, srcCl

Terminal Assignments and Signal Descriptions 1-101.6 Terminal Assignments and Signal DescriptionsTable 1–1. Signal and Pad Descriptions for the C614SI

Individual Instruction Descriptions 4-1684.14.73 SHLTPL Shift Left and Transfer PL to AccumulatorSyntax[label] name dest, src [, mod] Clock, clkWord,

Individual Instruction Descriptions4-169Assembly Language Instructions4.14.74 SHLTPLS Shift Left String and Transfer PL to AccumulatorSyntax[label] na

Individual Instruction Descriptions 4-1704.14.75 SHRAC Shift Accumulator RightSyntax[label] name dest, src, [, mod] Clock, clkWord, wWith RPT, clkClas

Individual Instruction Descriptions4-171Assembly Language Instructions4.14.76 SHRACS Shift Accumulator String RightSyntax[label] name dest, srcClock,

Individual Instruction Descriptions 4-1724.14.77 SOVM Set Overflow ModeSyntax[label] nameClock, clkWord, wWith RPT, clkClassSOVM 1 1 N/R 9dExecution S

Individual Instruction Descriptions4-173Assembly Language Instructions4.14.78 STAG Set TagSyntax[label] name destClock, clkWord, wWith RPT, clkClassST

Individual Instruction Descriptions 4-1744.14.79 SUB SubtractSyntax[label] name dest, src, src1, [next A]] Clock, clkWord, wWith RPT, clkClassSUB An[~

Individual Instruction Descriptions4-175Assembly Language InstructionsSyntax DescriptionSUB An[~], An, {adrs} [, next A] Subtract effective data memor

Individual Instruction Descriptions 4-1764.14.80 SUBB Subtract ByteSyntax[label] name dest, srcClock, clkWord, wWith RPT, clkClassSUBB An, imm81 1 N/R

Individual Instruction Descriptions4-177Assembly Language Instructions4.14.81 SUBS Subtract Accumulataor StringSyntax[label] name dest, src, src1Clock

Terminal Assignments and Signal Descriptions1-11Introduction to the MSP50C614The C614 is sold in die form for its volume production. Contact you local

Individual Instruction Descriptions 4-178Syntax DescriptionSUBS An[~], An, {adrs} Subtract data memory string from An string, store result in An[~] st

Individual Instruction Descriptions4-179Assembly Language Instructions4.14.82 SXM Set Extended Sign ModeSyntax[label] nameClock, clkWord, wWith RPT, c

Individual Instruction Descriptions 4-1804.14.83 VCALL Vectored CallSyntax[label] name destClock, clkWord, wWith RPT, clkClassVCALLvector82 1 N/R 7aEx

Individual Instruction Descriptions4-181Assembly Language Instructions4.14.84 XOR Logical XORSyntax[label] name dest, src, src1 [, mod] Clock, clkWord

Individual Instruction Descriptions 4-182See Also XORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, NOTACSExample 4.14.84.1 XOR A1, A1, 0x13FFXOR immediate

Individual Instruction Descriptions4-183Assembly Language Instructions4.14.85 XORB Logical XOR ByteSyntax[label] name dest, srcClock, clkWord, wWith R

Individual Instruction Descriptions 4-1844.14.86 XORS Logical XOR StringSyntax[label] name dest, src [, src1] Clock, clkWord, wWith RPT, clkClassXORS

Individual Instruction Descriptions4-185Assembly Language Instructions4.14.87 ZAC Zero AccumulatorSyntax[label] name dest [, mod] Clock, clkWord, wWit

Individual Instruction Descriptions 4-1864.14.88 ZACS Zero Accumulator StringSyntax[label] name destClock, clkWord, wWith RPT, clkClassZAC AnnS+3 1 nR

Instruction Set Encoding4-187Assembly Language Instructions4.15 Instruction Set EncodingInstructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0ADD An[~]

Terminal Assignments and Signal Descriptions 1-12Figure 1–4. MSP50C614 100 Pin PJM PLastic Package Pinout (Preliminary Information)1234567891011121314

Instruction Set Encoding 4-188Instructions 012345678910111213141516CMP An, {adrs}0 1 0 1 1 0 0 An adrsxdma16 (for direct) or offset16 (long relative)

Instruction Set Encoding4-189Assembly Language InstructionsInstructions 012345678910111213141516JMP pma16, Rx––1 0 0 0 0 0 0 1 0 1 0 1 Rx1 0xpma16JMP

Instruction Set Encoding 4-190Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0MOV PH, {adrs}1 1 0 1 1 0 0 0 1adrsxdma16 (for direct) or offset16

Instruction Set Encoding4-191Assembly Language InstructionsInstructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0MOVB {adrs}, Anxdma16 (for direct) or

Instruction Set Encoding 4-192Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0MUL {adrs}1 1 0 1 1 1 0 1 1adrsxdma16 (for direct) or offset16 (lo

Instruction Set Encoding4-193Assembly Language InstructionsInstructions 012345678910111213141516ORS An[~], An[~], pma161 1 1 0 0 1 1 An1 0 0 0 0 1 A~

Instruction Set Encoding 4-194Instructions 012345678910111213141516SHLTPLS An[~], An[~] 1 1 1 0 0 1 1 An1 1 0 1 0 0 A~ ~ASHLAC An[~], An[~] [, next A

Instruction Set Encoding4-195Assembly Language InstructionsInstructions 012345678910111213141516ZAC An[~] [, next A] 1 1 1 0 0next AAn0 0 0 1 1 0 0 ~

Instruction Set Summary 4-1964.16 Instruction Set SummaryUse the legend in Section 4.13 and the following table to obtain a summary ofeach instruction

Instruction Set Summary4-197Assembly Language InstructionsnameClassWith RPT, clkWords, wClock, clkdest [, src] [, src1] [,mod]CMP Rx, imm162 2 N/R 2bC

Terminal Assignments and Signal Descriptions1-13Introduction to the MSP50C614For software development and prototyping, a windowed ceramic 120-pin grid

Instruction Set Summary 4-198nameClassWith RPT, clkWords, wClock, clkdest [, src] [, src1] [,mod]MOV {adrs}, An[~] [, next A]Table 4–46Table 4–46 1aMO

Instruction Set Summary4-199Assembly Language Instructionsnamedest [, src] [, src1] [,mod]Clock, clkWords, wWith RPT, clkClassMOV {adrs}, SVTable 4–46

Instruction Set Summary 4-200name dest [, src] [, src1] [,mod]Clock, clkWords, wWith RPT, clkClassMOVU MR, {adrs}Table 4–46Table 4–46 5MOVAPH An, MR,

Instruction Set Summary4-201Assembly Language InstructionsnameClassWith RPT, clkWords, wClock, clkdest [, src] [, src1] [,mod]OR TFn, {flagadrs} 1 1 n

Instruction Set Summary 4-202nameClassWith RPT, clkWords, wClock, clkdest [, src] [, src1] [,mod]SHLTPLS An, {adrs}Table 4–46Table 4–46 1bSHLTPLS An[~

Instruction Set Summary4-203Assembly Language InstructionsnameClassWith RPT, clkWords, wClock, clkdest [, src] [, src1] [,mod]XORS An, {adrs}Table 4–4

Instruction Set Summay4-204Assembly Language InstructionsMSP50C614 (MSP50P614) IO Port DescriptionAddress Bits Name R/W 15 14 13 12 11 10 9 8 7 6 5 4

Instruction Set Summay4-205Assembly Language InstructionsMSP50C614 (MSP50P614) IO Port DescriptionAddress Bits Name R/W 15 14 13 12 11 10 9 8 7 6 5 4

Instruction Set Summay4-206Assembly Language InstructionsInterrupt Vector Source Trigger Event Priority CommentINT0 0x7FF0 DAC Timer timer underflow h

Instruction Set Summay4-207Assembly Language Instructions10 kHz Nominal Synthesis Rate (32.768 kHz oscillator reference)ClkSpdCtrlMasterCPUOutputNumbe

iiiRead This FirstPrefaceRead This FirstAbout This ManualThis user’s guide gives information for the MSP50C61 mixed-signal proces-sor. This informatio

Terminal Assignments and Signal Descriptions 1-14The pin assignments for the 120-pin PGA package (P614 device only) are out-lined in the following tab

Instruction Set Summay4-208Assembly Language Instructions

5-1Code Development ToolsFor code development purposes, the programmable MSP50P614 is used.The MSP50C6xx code development tool is used to compile, lin

Introduction 5-25.1 IntroductionThe MSP50C6xx development tools gain access to the core controller via aserial scan interface called the Scanport. The

MSP50C6xx Software Development Tool5-3Code Development Toolsthe reset circuit and the reset pin, and connecting the scanport reset signaldirectly to t

Requirements 5-45.3 RequirementsThe requirements for a complete MSP50C6xx development system are asfollows:PC Requirements:Intel i486 or Pentium cla

Hardware Installation5-5Code Development Tools5.4 Hardware InstallationThe following steps are used to set up the hardware (see Figure 5–2):1) Connect

Software Installation 5-6Figure 5–3. 10-Pin IDC Connector (top view looking at the board)IDC2X5MRESETVPPSCANCLKPGMPULSESYNCGNDN/CSCANINVDDSCANOUT13579

Software Installation5-7Code Development ToolsFigure 5–5. Setup WindowStep 2: After setup runs the InstallShield (see Figure 5–4), the setup windowpop

Software Installation 5-8Figure 5–6. Exit Setup DialogStep 4: If you press Cancel, you can return to setup by pressing Resume but-ton. You can exit se

Software Installation5-9Code Development ToolsStep 5: If you continue with setup, you will be brought to User Informationdialog. Enter your Name and C

2-1MSP50C614 ArchitectureA detailed description of MSP50C614 architecture is included in this chapter.After reading this chapter, the reader will have

Software Installation 5-10Figure 5–9. Select Program Folder DialogStep 9: Enter a new folder name in Select Program Folder dialog.Step 10: Press Next

Software Installation5-11Code Development ToolsFigure 5–10. Copying FilesStep 11: The program starts installation. When the installation is complete,

Software Installation 5-12Figure 5–11.Setup Complete DialogStep 12: The Setup Complete dialog message is displayed when setup iscompleted. Press the F

Software Emulator5-13Code Development Tools5.6 Software EmulatorRun the EMUC6xx.exe program which will be in the installation directory oron your desk

Software Emulator 5-14Figure 5–13. Project MenuFigure 5–14. Project Open Dialog

Software Emulator5-15Code Development ToolsFigure 5–15. File Menu Options5.6.2 ProjectsThe emulator can only work from project files created within th

Software Emulator 5-16(pfe32.exe) and an error dialog. The user can modify the source code andsave the changes, before restarting the building action.

Software Emulator5-17Code Development ToolsFigure 5–17. RAM WindowRAM Window : Displays 16-bit data memory hex values. The left most columnis the addr

Software Emulator 5-18Watch Window : Watch window displays the data memory location and datato be watched. It mirrors the value displayed in the RAM w

Software Emulator5-19Code Development Toolsbeing run in emulation mode. STK field is the depth of the stack. The emulatorkeeps track of number of call

2-22.1 Architecture OverviewThe core processor in the C614 is a medium performance mixed signal pro-cessor with enhanced microcontroller features an

Software Emulator 5-20background is the line reached by a search command (by PC, line number orlabel). Search position can also be set by double click

Software Emulator5-21Code Development Toolsvariable value and its address in RAM are then displayed (Figure 5–21).Variables appearing on a gray backgr

Software Emulator 5-22modified (i.e, by double clicking on a value and typing its new hexadecimalvalue over the existing value). Values of read only r

Software Emulator5-23Code Development ToolsStep Over : This menu option, (key equivalent: F8), allows the user to stepover a call instruction in the p

Software Emulator 5-24Fast Run : This menu option, (key equivalent: CTRL+F9), allows the user toexecute a portion of the program window, until a break

Software Emulator5-25Code Development ToolsFigure 5–25. EPROM Programming Dialog

Software Emulator 5-26Trace Mode : This menu option launches the Trace Mode Dialog(Figure 5–25), that allows that user to run the chip in trace mode,

Software Emulator5-27Code Development ToolsStop Internal : This menu option halts execution of an internal program. Itprovides an internal picture of

Software Emulator 5-28Init RAM : Initializes the data memory values to zero including tag bits.Init Registers : Initializes all the system registers (

Software Emulator5-29Code Development ToolsFigure 5–28. Options MenuFigure 5–29. Miscellaneous DialogList of directories separated bysemicolons that t

2-3MSP50C614 ArchitectureFigure 2–1. MSP50C614 Core Processor Block DiagramMultiplier (MR)† Shift Value (SV)†17 x 17 MultiplierProduct High (PH)†16 b

Software Emulator 5-30Figure 5–30. Windows Menu Options5.6.7 Emulator Online Help SystemThe emulator has an online help which is launched when the Hel

Software Emulator5-31Code Development ToolsFigure 5–31. Context Sensitive Help System

Software Emulator 5-325.6.8 Known Differences, Incompatibilities, RestrictionsInclude statements in assembly language files must enclose the file name

Assembler5-33Code Development Tools5.7 AssemblerThe MSP50P614/MSP50C614 assembler is implemented as a Windows DLL(Dynamic Linked Library).5.7.1 Assemb

Assembler 5-345.7.2 Assembler DirectivesAssembler directives are texts which have special meaning to the assembler.Some of these directives are extrem

Assembler5-35Code Development Toolssymbol is any alphanumeric text starting with an alphabetic character, anumber, or an expression.Examples:SYM1 EQU

Assembler 5-36Example:#IF expression; do something here#ELSE; do other things here#ENDIF#IFDEF symbol: Start of a conditional assembly structure. If s

Assembler5-37Code Development ToolsBYTE expression[,expression]: Introduces one or more data items, of BYTEsize (8 bits) . The bytes are placed in the

Linker 5-38should be declared there as EXTERNAL (or REF). Note that this technique canalso be used to make constants defined with the EQU statement av

C– – Compiler5-39Code Development ToolsThe syntax of the call is:extern int FAR PASCAL LINK_MAIN (LPSTR source_file,LPSTRexe_file);...ierr=LINK_MAIN

2-4Figure 2–2. Computational Unit Block Diagram (The shaded boxes represent internalprogrammable registers.)Accumulators516AC3AC2AC1AC0Read/WriteAC7

C– – Compiler 5-40short ram_size; /* ram size for the chip */short verbose; /* refers to assembly code output */short c_code; /* if non zero, c code i

C– – Compiler5-41Code Development Tools5.9.2 Variable TypesType Name Mnemonic Range Size in Bytes ExampleInteger int [–32768,32767] 2 int i,j;Characte

C– – Compiler 5-425.9.4 C– – DirectivesC– – has a limited number of directives and some additional directives notfound in ANSI C compilers. The follow

C– – Compiler5-43Code Development Tools5.9.4.3 #includeAs in regular C, this directive allows for the insertion of a file into the currentfile. If the

C– – Compiler 5-445.9.5 Include FilesThere are currently two include files supplied with C– –, cmm_func.h, whichcontains function prototypes for the C

C– – Compiler5-45Code Development Tools5.9.6 Function Prototypes and DeclarationsAs mentioned above,C– – function prototypes and declarations MUST be

C– – Compiler 5-46Table 5–1. String Functionsadd_string(int *result,int *str1,int *str2,int lg)adds strings str1 and str2, of length lg (+2),and puts

C– – Compiler5-47Code Development ToolsAlso note that the user has to supply the length of the input string and the lengthof the output string in the

Implementation Details 5-485.10 Implementation DetailsThis section is C– – specific.5.10.1 ComparisonsWe use the CMP instruction for both signed and u

Implementation Details5-49Code Development ToolsUnsigned comparison of a and b. (a is in A0, b is in A0~)Assembly Test Condition_ult a < b AULT_ule

Computation Unit2-5MSP50C614 Architecture2.2 Computation UnitThe computational unit (CU) is comprised of a (17-bit by 17-bit) Booth’salgorithm multipl

Implementation Details 5-505.10.2 DivisionThe integer division currently requires the use of several accumulator pointers.We divide a 16 bit integer l

Implementation Details5-51Code Development ToolsFunction declarations ( or function prototypes) are introduced by themnemonic cmm_func. We only allow

Implementation Details 5-52constant int M1[4]={0x04CB,0x71FB,0x011F,0x0};constant int M2[4]={0x85EB,0x8FD9,0x08FB,0x0};cmm_func string_multiply(int *p

Implementation Details5-53Code Development Toolsfree(mm2);free(pp);}cmm_func main(int argc,char *argv){int m1[4],m2[4],product[9];xfer_const(m1,M1,STR

Implementation Details 5-54find the correct size for bogus. Bogus can be made larger for extra safety aslong as enough memory is left over for the C––

Implementation Details5-55Code Development Tools|||||||––––––––––––––| |––––––––––––––| |––––––––––––––|| |R7 | |R5,R7 | ||––––––––––––––| |––––––––––

Implementation Details 5-56C to C function return (in cmm_return).|||||||||||||––––––––––––––| |––––––––––––––| |––––––––––––––|R5|||||||–––––––––––––

Implementation Details5-57Code Development Tools|––––––––––––––||||––––––––––––––||||––––––––––––––||||––––––––––––––||(old)R5 ||––––––––––––––||(old)

Implementation Details 5-58C to ASM function call. The stack is shown after the operation on the bottomis performed.|||||||––––––––––––––| |––––––––––

Implementation Details5-59Code Development Tools|||––––––––––––––||||––––––––––––––||||||––––––––––––––||||––––––––––––––|R7 |Return Addr ||––––––––––

Computation Unit 2-6The multiplicand source can be either data memory, an accumulator, or anaccumulator offset. The multiplier source can be either th

Implementation Details 5-60To call an assembly routine from C––, the routine must be defined as GLOBALin the assembly file and as a CMM_FUNC in the C–

Implementation Details5-61Code Development Tools;–––––––––––––––––––––––––––––––––––––––––––––––––––––; called from C––; void oport(char Port, int Dat

Implementation Details 5-62_iprtcin a0, 0x10 ; read from PortCret_iprtdin a0, 0x18 ; read from PortDret_iprtein a0, 0x20 ; read from PortEret_iprtf

Implementation Details5-63Code Development ToolsDATA _cprte;–––––––––––––––––––––––––––––––––––––––––––––––––––––;––––––––––––––––––––––––––––––––––––

Implementation Details 5-64nopret;****************************************************************; Dummy interrupt routines;*************************

Implementation Details5-65Code Development Toolscmm_func iport(int x); // read a portint i,j,k,l; // various temp and loop variablesint x[4]; // ar

Implementation Details 5-66 wait(100); oport(’B’, 0x00); wait(100); oport(’B’, 0xFF); wait(100); oport(’B’, 0x00);

Beware of Stack Corruption5-67Code Development Tools5.11 Beware of Stack CorruptionMSP50C614/MSP50P614 stack (pointed by R7 register) can easily get c

5-68

6-1ApplicationsThis chapter contains application information on application circuits, proces-sor initialization sequence, resistor trim setting, synth

Computation Unit2-7MSP50C614 ArchitectureFigure 2–3. Overview of the Multiplier Unit OperationMULTIPLIER UNIT INPUTSMultiplicand 16-bit- latched in a

Application Circuits 6-26.1 Application CircuitsTo pin 2 of Scan Port Connector†MSP50C614/MSP50P614To pin 1 of Scan Port Connector†(optional )5 V0.1 µ

Application Circuits6-3ApplicationsIt is of particular importance to provide a separate decoupling capacitor for theVDD, VSS pair which services the D

MSP50C614/MSP50P614 Initialization Codes 6-4In any C614 application, it is important for certain components to be locatedas close as possible to the C

MSP50C614/MSP50P614 Initialization Codes6-5Applications6.2.1 File init.asm;****************************************************************; INIT.ASM;

MSP50C614/MSP50P614 Initialization Codes 6-6 out IntGenCtrl,a0 ;clear all interrupt mask bits, disabletimers mov r0,0x0

MSP50C614/MSP50P614 Initialization Codes6-7Applications mov *save_clkspdctrl,a0 ;save the ClkSpdCtrl value for later, when

Texas Instruments C614 Synthesis Code 6-86.3 Texas Instruments C614 Synthesis CodeSome sample codes are supplied with the development tools. These sam

Texas Instruments C614 Synthesis Code6-9ApplicationsTo continue, click on the Run Internal icon again. The LEDs should flash duringMELP synthesis (Ext

Texas Instruments C614 Synthesis Code 6-10| spk_ram.irx|| –––––––– melp| melp.obj| melp.irx|–––––––– modules| –––––––– 605| 605.asm| 605.irx|| –––––––

Texas Instruments C614 Synthesis Code6-11ApplicationsFile DescriptionUtil.obj Maths functions and tables used by the vocoders.Dsputil.asm Oversampling

Computation Unit 2-8The all-zero values are necessary for data transfers and unitary operations.All-zeros also serve as default values for the registe

Texas Instruments C614 Synthesis Code 6-12RAM UsageThe file MAIN.LST contains the variable RAM assignments. Do a search forBEGIN_RAM to find the start

Texas Instruments C614 Synthesis Code6-13ApplicationsThese files may be edited for special purpose codeINIT.ASM and SPEAK.ASMThese files should never

ROM Usage With Respect to Various Synthesis Algorithms 6-146.4 ROM Usage With Respect to Various Synthesis AlgorithmsThe following table lists some po

7-1Customer InformationCustomer information regarding package configurations, development cycle,and ordering forms are included in this chapter.Topic

Mechanical Information 7-27.1 Mechanical InformationThe C614 is normally sold in die form but is also available in 100-pin PJMpackages. The P614 is av

Mechanical Information7-3Customer Information7.1.2 Package InformationThe MSP50C614 will be available in the 100-pin PJM package (seeFigure 7–1 and Ta

Mechanical Information 7-4Figure 7–1. 100-Pin PJM Mechanical Information4040022/B 03/950,16 NOM14,20 17,4513,80 16,955051313012,35 TYP1,030,730,25Seat

Mechanical Information7-5Customer InformationThe C614 is sold in die form for its volume production. For software develop-ment and prototyping, a wind

Mechanical Information 7-6The pin assignments for the 120-pin PGA are outlined in the following table.(Refer to Section 1.6 for more information on th

Customer Information Fields in the ROM7-7Customer Information7.2 Customer Information Fields in the ROMIn those cases where the customer code is progr

Computation Unit2-9MSP50C614 ArchitectureFigure 2–4. Overview of the Arithmetic Logic UnitALU INPUTSALU-A 16-bit- selects between ...all 0’sOffset Acc

Speech Development Cycle 7-87.3 Speech Development CycleFigure 7–4. Speech Development CycleSpeech SpecificationSpeaker SelectionRecording ScriptPrepa

Device Production Sequence7-9Customer InformationAll prototype devices are shipped with the following disclaimer: It is understoodthat, for expediency

Ordering Information 7-107.5 Ordering InformationBecause the MSP50C614 is a custom device, it receives a distinct identifica-tion, as follows:CSMGate

New Product Release Forms7-11Customer InformationNEW PRODUCT RELEASE FORM FOR MSP50C614 (DIE ONLY)SECTION 1. ORDER INFORMATIONDivision:_______________

7-12

A-1Appendix AMSP50C605 Preliminary DataThis Appendix contains preliminary data for the MSP50C605 device.Note: MSP50C605MSP50C605 is in the Product Pre

Introduction A-2A.1 IntroductionMSP50C605 is a spin off of the core processor MSP50C614. It uses three IOports of MSP50C614 and maps a 1.835 Mbits of

ArchitectureA-3MSP50C605 Preliminary DataA.3.1 RAMThe MSP50C605 (like MSP50C614) has 640 17-bit words of internal datamemory (static RAM). This RAM oc

Architecture A-4Figure A–1. MSP50C605 ArchitectureData ROM access Core CU Computational Unit PCU Prog. Counter Unit Instr. DecoderTIMER1 PRD1 TI

ArchitectureA-5MSP50C605 Preliminary DataFigure A–2. MSP50C605 Memory Organization0x00000x08000x07FF0x7FF00x7FF7User ROM30704 x 17 bit(C605 : read–o

Notational Conventionsiv version of the special typeface for emphasis; interactive displays use abold version of the special typeface to distinguish c

Computation Unit 2-10When writing an accumulator-referenced instruction, therefore, the workingaccumulator address is stored in one of AP0 to AP3. The

Architecture A-6Figure A–3. MSP50C605 100-Pin PJM PackageMSP50C605 100 PIN PJMPLASTIC PACKAGE1808110030315051

ArchitectureA-7MSP50C605 Preliminary DataTable A–1. MSP50C605 100-Pin PJM Plastic Package Pinout DescriptionDescription Pin# Description Pin# Descript

A-8

B-1Appendix AMSP50C604 Preliminary DataThis Appendix contains preliminary data for the MSP50C604 device.Note: MSP50C604MSP50C604 is in the Product Pre

Introduction B-2B.1 IntroductionMSP50C604 is a spin off of the core processor MSP50C614. It is targeted asa slave device. An external microprocessor i

ArchitectureB-3MSP50C604 Preliminary DataB.3.1 RAMThe MSP50C604 (like MSP50C614) has 640 17–bit words of internal datamemory (static RAM). This RAM oc

Architecture B-4Figure B–1. MSP50C604 Block Diagram Core CU Computational Unit PCU Prog. Counter Unit Instr. DecoderTIMER1 PRD1 TIM10x3A 0x3B Cl

ArchitectureB-5MSP50C604 Preliminary DataB.3.4 Slave Mode OperationThe MSP50C604 is used as a peripheral device in slave mode. A microproces-sor/micro

Architecture B-6Figure B–2. MSP50C604 Memory Organization and I/O ports0x00000x08000x07FF0x7FF00x7FF7User ROM30704 x 17 bit(C604 : read–only) (P61

ArchitectureB-7MSP50C604 Preliminary DataB.3.7 InterruptsInterrupts for MSP50C604 are the same as MSP50C614 in host mode exceptINT5 (port F interrupt)

Data Memory Address Unit2-11MSP50C614 ArchitectureFor some instructions, the 5-bit string processor can also preincrement orpredecrement the AP pointe

Packaging B-8B.4 PackagingThe MSP50C604 is sold in die form. A 64 pin plastic package is also available.Table B–1. MSP50C604 64-Pin PJM Plastic Packag

PackagingB-9MSP50C604 Preliminary DataFigure B–3. MSP50C604 Slave Mode SignalsINRDYOUTRDYR/WZSTROBEPC0–PC7Data latched to Port ANew DataValid DataHost

Packaging B-10

C-1Appendix AMSP50C605 Data SheetThis appendix contains the data sheet for the MSP50C605 mixed-signal pro-cessor.Topic PageC.1 MSP50C605 Data Sheet C–

C-2C.1 MSP50C605 Data SheetThis appendix contains the data sheet for the MSP50C605 mixed-signal pro-cessor.

Data Memory Address Unit 2-12Figure 2–6. Data Memory Address UnitR3R2R1R0R7R6R5R4InternalDatabusArithmetic BlockRAM AddressInternal Program BusRegiste

Data Memory Address Unit2-13MSP50C614 ArchitectureThere are two-byte instructions, for example MOVB, which cause the proces-sor to read or write data

Program Counter Unit 2-142.4 Program Counter UnitThe program counter unit provides addressing for program memory (onboardROM). It includes a 16-bit ar

Memory Organization: RAM and ROM2-15MSP50C614 Architecture2.6 Memory Organization: RAM and ROMData memory (RAM) and program memory (ROM) are each rest

Memory Organization: RAM and ROM 2-16Figure 2–7. C614 Memory Map (not drawn to scale)0x00Program Memory0x0000Internal Test Code2048 x 17 bit0x07FF0x08

Memory Organization: RAM and ROM2-17MSP50C614 ArchitectureWhen writing to any of the locations in the I/O address map, therefore, thebit-masking need

Memory Organization: RAM and ROM 2-18Table 2–2. Summary of C614’s Peripheral Communications Ports (Continued)I/O MapAddressWidth ofLocationAllowableA

Memory Organization: RAM and ROM2-19MSP50C614 Architecture3.1.5, Internal and External Interrupts, for more information regarding thespecific conditio

Information About Cautions and WarningsvRead This FirstUnless the list is enclosed in square brackets, you must choose one itemfrom the list.Some dire

Memory Organization: RAM and ROM 2-20The protection modes are implemented on the C614 as follows. Within theROM is a dedicated storage for the block p

Memory Organization: RAM and ROM2-21MSP50C614 Architecture[(NTM + 1) * 512 – 1] = highest ROM address within the block to beprotected(NTM + 1) * 512 =

Interrupt Logic 2-22When the device is powered up, the hardware initialization circuit reads thevalue stored in the block protection word. The value i

Interrupt Logic2-23MSP50C614 Architecturethe RESET low, assuming there is no interruption in power. For a fulldescription of the interrupt-trigger eve

Interrupt Logic 2-24Note: Setting a Bit in the IFR Using the OUT InstructionSetting a bit within the IFR using the OUT instruction is a valid way of o

Interrupt Logic2-25MSP50C614 ArchitectureFigure 2–8 provides an overview of the interrupt control sequence. INT0 is thehighest priority interrupt, and

Timer Registers 2-26In addition to being individually enabled, all interrupts must be GLOBALLYenabled before any one can be serviced. Whenever interru

Timer Registers2-27MSP50C614 Architecture(16-bit wide location)15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00PRD1 register†address 0x3APPPPPPPPPPPPPP

Timer Registers 2-28Selection between the timer-source options is made using two control bits inthe interrupt/general control register (IntGenCtrl). T

Clock Control2-29MSP50C614 Architecture2.9 Clock Control2.9.1 Oscillator OptionsThe C614 has two oscillator options available. Either option may be en

vi

Clock Control 2-30The maximum required CPU clock frequency for the C614 is 8 MHz over theentire VDD range. This rate applies to the speed of the core

Clock Control2-31MSP50C614 ArchitectureNote: ClkSpdCtrl Bits 8 and 9When bit 8 is set in the ClkSpdCtrl register, the crystal oscillator bit (bit 9) b

Clock Control 2-32Bit 10 in the ClkSpdCtrl is idle state clock control. The level of deep-sleepgenerated by the IDLE instruction is partially controll

Execution Timing2-33MSP50C614 ArchitectureHowever, the general specification of the adjustment can be useful in certaincircumstances. For example, the

Reduced Power Modes 2-34Figure 2–10. Instruction Execution and TimingNN+1 N+2N+3N+4N+5 N+6N+7FETCHCLOCKN–1N N+1N+2N+3N+4 N+5DECODEN–2N–1 NN+1N+2N+3 N+

Reduced Power Modes2-35MSP50C614 ArchitectureThe deepest sleep achievable on the C614, for example, is a mode where allof the previously listed subsyt

Reduced Power Modes 2-36The power consumed during sleep when the RTO oscillator is left running isgreater than the power consumed during sleep when th

Reduced Power Modes2-37MSP50C614 ArchitectureTable 2–3. Programmable Bits Needed to Control Reduced Power Modes→ deeper sleep … relatively less powe

Reduced Power Modes 2-38Table 2–4. Status of Circuitry When in Reduced Power Modes (Refer to Table 2–3)→ deeper sleep … relatively less power →Com

Reduced Power Modes2-39MSP50C614 ArchitectureThe interrupt-trigger event associated with each of the two internal TIMERs isthe underflow condition of

ContentsviiContents1 Introduction to the MSP50C614 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reduced Power Modes 2-40In order to wake the device using a programmable interrupt, the interrupt maskregister must have the respective bit set to ena

3-1Peripheral FunctionsThis chapter describes in detail the MSP50C614 peripheral function, i.e., I/Ocontrol ports, general purpose I/O ports, interrup

I/O 3-23.1 I/OThe C614 has 64 input-output pins. Forty of these are software configurable aseither inputs or outputs. Eight are dedicated inputs, and

I/O3-3Peripheral Functionsis 0x00 (all inputs). The state of the data registers after RESET low is unknown(input state provided by external hardware).

I/O 3-43.1.2 Dedicated Input Port FPort F is an 8-bit wide input-only port. The data presented to the input pin canbe read by referring to the appropr

I/O3-5Peripheral Functions3.1.3 Dedicated Output Port GPort G is a 16-bit wide output-only port. The output drivers have a Totem-Poleconfiguration. Th

I/O 3-63.1.4 Branch on D PortInstructions exist to branch conditionally depending upon the state of ports D0and D1. These conditionals are COND1 and C

I/O3-7Peripheral FunctionsRegisters). INT1 and INT2 are high-priority, internal interrupts triggered by theunderflow conditions on TIMER1 and TIMER2,

Digital-to-Analog Converter (DAC) 3-83.2 Digital-to-Analog Converter (DAC)The C614 incorporates a two-pin pulse-density-modulated DAC which iscapable

Digital-to-Analog Converter (DAC)3-9Peripheral FunctionsDAC Control registerAddress 0x34 (4-bit wide location)03 02 01 00Set DAC resolution t

Contentsviii 3.1.1 General-Purpose I/O Ports 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 Dedicate

Digital-to-Analog Converter (DAC) 3-10style. Their selection is made at bit 3 of the DAC control register (0x34). TheC3x style is selected by clearing

Digital-to-Analog Converter (DAC)3-11Peripheral FunctionsFor a given sampling rate and DAC resolution, the CPU clock rate may beincreased, if necessar

Digital-to-Analog Converter (DAC) 3-128 kHz Nominal Synthesis Rate32.768 kHz Oscillator ReferenceDACPrecisionIntGenCtrlPDMCDBitOver-SamplingFactorClkS

Digital-to-Analog Converter (DAC)3-13Peripheral Functions10 kHz Nominal Synthesis Rate32.768 kHz Oscillator ReferenceDACPrecisionIntGenCtrlPDMCDBitOve

Comparator 3-143.3 ComparatorThe C614 provides a simple comparator that is enabled by a control registeroption. The inputs of the comparator are share

Comparator3-15Peripheral Functionsbit is automatically CLEARed again if an INT6 event occurs at the same timethat the associated mask bit is SET (IntG

Comparator 3-16The comparator, along with all of its associated functions, is enabled by settingbit 15 of the interrupt/general control register (IntG

Interrupt/General Control Register3-17Peripheral Functions3.4 Interrupt/General Control RegisterThe interrupt/general control (IntGenCtrl) is a 16-bit

Interrupt/General Control Register 3-18The upper four bits in the IntGenCtrl have independent functions. Bit 12 is theenable bit for the pull-up resis

Hardware Initialization States3-19Peripheral Functions3.5 Hardware Initialization StatesThe RESET pin is configured at all times as an external interr

ContentsixContents4.4.8 Class 8 Instructions: Logic and Bit 4-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.9 Class 9

Hardware Initialization States 3-20Note: Internal RAM State after ResetThe RESET low will not change the state of the internal RAM, assuming thereis n

Hardware Initialization States3-21Peripheral FunctionsNote: Stack Pointer InitializationThe software stack pointer (R7) must be initialized by the pro

3-22

4-1Assembly Language InstructionsThis chapter describes in detail about MSP50P614/MSP50C614 assemblylanguage. Instruction classes, addressing modes, i

Introduction 4-24.1 IntroductionIn this chapter each MSP50P614/MSP50C614 class of instructions isexplained in detail with examples and restrictions. M

System Registers4-3Assembly Language Instructionsor by 2 for double word instructions) each execution cycle and points to thenext program memory locat

System Registers 4-4It is recommended to avoid using the TOS register altogether in applicationsand leave its operation to development tools only.4.2.

System Registers4-5Assembly Language InstructionsDuring accumulator read operations, both An and offset An~ are fetched.Depending on the instruction,

System Registers 4-6value of the STACK register should be stored before use and restored afteruse. This register must point to the beginning of the st

System Registers4-7Assembly Language InstructionsTable 4–1. Status Register (STAT)Bit Name Function0 XM Sign extended mode bit. This bit is one, if si