Texas-instruments TMS320C6455 Manual do Utilizador descarregar pdf (Página 33)

DDR2CLKOUT

DSDCKE

DCE0

DSDWE

DSDRAS

DSDCAS

DSDDQM0

DSDDQM1

DSDDQS0

DSDDQS1

DBA[2:0]

DEA[13:0]

DED[15:0]

REFSSTL

ODT0

DSDDQS0

DSDDQS1

CKE

RAS

CAS

LDM

UDM

LDQS

UDQS

BA[2:0]

A[12:0]

DQ[15:0]

ODT

REF

LDQS

UDQS

DDR2

Memory

x16-bit

REF

DDR2

Memory

Controller

ODT1

DSDDQGATE0

(A)

DSDDQGATE1

(A)

DSDDQGATE2

(A)

DSDDQGATE3

(A)

DDRSLRATE

www.ti.com

Using the DDR2 Memory Controller

Figure 17. Connecting to a Single 16-Bit DDR2 SDRAM Device

A These pins are used as a timing reference during memory reads. For routing rules, see the device-specific data

manual.

SPRU970G– December 2005– Revised June 2011 C6455/C6454 DDR2 Memory Controller

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1 2 ... 28 29 30 31 32 33 34 35 36 37 38 ... 49 50

User's Guide 1
Submit Documentation Feedback 2
Contents 3
Read This First 7
Introduction 10
2 Peripheral Architecture 11
2.1 Clock Control 11
2.2 Memory Map 11
2.3 Signal Descriptions 11
Peripheral Architecture 12
2.4 Protocol Description(s) 13
Figure 7. DEAC Command 18
2.6 Address Mapping 21
2.8 Refresh Scheduling 27
2.9 Self-Refresh Mode 28
2.10 Reset Considerations 28
2.12 Interrupt Support 30
2.13 EDMA Event Support 30
2.14 Emulation Considerations 30
Reserved Rsvd Rsvd RL 48
Revision History 49
IMPORTANT NOTICE 50

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