Texas Instruments MSC1210 Manual do Utilizador

      December 2002User’s GuideSBAU077

Contentsviii16−1. Rotate Operations 16-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Setting the Serial Port Mode9-10Figure 9−6. Serial Port 0 Mode 2 Receive Timing.Transmission is initiated by any instruction that writes to SBUF. The

Setting the Serial Port Mode9-11Serial Communication9.2.4 Serial Mode 3: Asynchronous Full-DuplexIn mode 3, serial data transfers are 11 bits, full-du

Setting the Serial Port Mode9-12Reception is enabled by configuring SCON0.RBN = 1. Reception of the databegins at the falling edge of start-bit detect

Setting the Serial Port Baud Rate9-13Serial Communication9.3 Setting the Serial Port Baud RateOnce the serial port mode has been configured, as explai

Setting the Serial Port Baud Rate9-14For example, with an 11.059MHz crystal, to configure the serial port to 19 200baud, try plugging it in the first

Writing to the Serial Port9-15Serial CommunicationTable 9−6.Baud Rate Settings for Timer 2.Baud Rate33MHz clk 25MHz clk 11.0592MHz clkBaud Rate(kb/s)C

Reading the Serial Port9-169.5 Reading the Serial PortReading data received by the serial port is equally easy. To read a byte fromthe serial port, ju

10-1Interrupts Chapter 10 describes the interrupts of the MSC1210 ADC.Topic Page10.1 Description 10-2. . . . . . . . . . . . . . . . . . . .

Description10-210.1 DescriptionAs the name implies, an interrupt is some event that interrupts normal programexecution. As stated previously, program

Events That Can Trigger Interrupts10-3InterruptsThus, every 65 536 instruction cycles, Timer 0 overflows and the CPL andRETI instructions are executed

Contentsix Contents1−1. Pin Descriptions of the MSC1210 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Events That Can Trigger Interrupts10-4In other words, the MSC1210 can be configured so that any of the events inTable 10−1, ranging from a simple Time

Enabling Interrupts10-5Interrupts10.3 Enabling InterruptsBy default, at power-up all interrupts are disabled. This means that even if, forexample, the

Polling Sequence10-6Each of the MSC1210 interrupts has its own enable bit in one of these threeSFRs. Enable a given interrupt by setting the correspon

Interrupt Priorities10-7Interrupts10.5 Interrupt PrioritiesThe MSC1210 offers three levels of interrupt priority: highest, high, and low.By using inte

Interrupt Triggering10-8When considering interrupt priorities, the following rules apply:1) Nothing can interrupt the highest-priority auxiliary inter

Types of Interrupts10-9Interrupts10.8 Types of InterruptsEach interrupt can be categorized as one these types: serial, external, timer,watchdog, or au

Types of Interrupts10-10Note:Level-sensitive interrupts are not latched. If the interrupt is level-sensitive,the condition must be present until the p

Types of Interrupts10-11Interrupts10.8.3 Timer InterruptsThe MSC1210 microcontroller incorporates three 16-bit programmable tim-ers, each of which can

Types of Interrupts10-12Table 10−8.Clearing Auxiliary InterruptsAux Interrupt Type Method to Clear InterruptSeconds interrupt Read SECINT SFRSummation

Types of Interrupts10-13InterruptsThe AISTAT (A7H) is a read-only SFR that returns the current state of interruptconditions that are enabled. Any cond

Contentsx14−1. Typical Sub-Circuit Current Consumption 14-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14−2. Compa

Types of Interrupts10-14The four bits, PAI0 through PAI3, make up a 4-bit value that indicates the auxil-iary interrupt that triggered the actual inte

Waking Up from Idle Mode10-15Interruptsa millisecond interrupt will be provoked every 20ms. This assumes and re-quires that MSECH (FDH) and MSECL (FCH

Register Protection10-1610.10 Register ProtectionOne very important rule applies to all interrupt handlers: interrupts must leavethe processor in the

Register Protection10-17InterruptsThe guts of the interrupt are the MOV instruction and the ADD instruction.However, these two instructions modify the

Common Problems with Interrupts10-1810.11 Common Problems with InterruptsInterrupts are a very powerful tool available to you, but when used incorrect

11-1Pulse Width Modulator/Tone Generator $ & ' (Chapter 11 describes the pulse width modulator/tone generator

Description11-211.1 DescriptionThe pulse width modulator (PWM) has two modes: one mode functions as atone generator and the the other mode functions a

Tone Generator11-3Pulse Width Modulator/Tone GeneratorThe three bits that together make up TPCNTL, control the function of the PWM/tone generator. The

Tone Generator11-411.2.1 Tone Generator WaveformsWhen TPCNTL[1:0] = 11, the output of the tone generator may be either a stair-case waveform or a squa

PWM Generator11-5Pulse Width Modulator/Tone Generator11.3 PWM GeneratorThe PWM generator is activated when TPCNTL[1:0] = 01. This setting allowsa PWM

1-1Introduction to the MSC1210    This chapter describes the basic function of the MSC1210 analog-to-digitalconverter (ADC)

PWM Generator11-6Figure 11−5. Timing Diagram of a PWM WaveformIn the timing diagram of a PWM waveform in Figure 11−5, the waveform is lowfor 2 ticks a

PWM Generator11-7Pulse Width Modulator/Tone GeneratorThis can be expressed in code as:PWMCON = 0x10; // Sel PWM Duty RegisterPWM = 128−1; // PWM toggl

PWM Generator11-811.3.1 Example of PWM Tone GenerationTable 11−2 illustrates configuring the PWM for tone generation, andTable 11−3 explains selected

PWM Generator11-9Pulse Width Modulator/Tone Generator11.3.2 Example of PWM Tone Generation IdlingWhen PWM is idling, system requirements for the PWM o

PWM Generator11-10Table 11−4.Configuring the PWM for Tone Generation with PWM IdlingStmt ‘C’ Source Code Assembly Source Code1 // PWM PUBLIC mainRSEG

PWM Generator11-11Pulse Width Modulator/Tone Generator11.3.3 Example of Updating PWMBoth PWM Period and PWM Duty, set via the PWMHI and PWMLOW SFRs,ar

PWM Generator11-12// PWM#include <REG1210.H>#define OneUsConst (2−1)#define CLEAR 0#define SET 1sbit p33=P3^3;sbit p14=P1^4;unsigned char p,d;vo

12-1Analog-to-Digital Converter #))* +Chapter 12 describes the ADC of the MSC1210.Topic Page12.1 Description 12-2. . . . . . . .

Description12-212.1 DescriptionThe MSC1210 includes an ADC with 24-bit resolution. The ADC consists ofan input multiplexer (MUX), an optional buffer,

Input Multiplexer12-3Analog-to-Digital Converter12.2 Input MultiplexerThe MSC1210 multiplexer is more flexible than a typical ADC in that each inputpi

MSC1210 Description1-21.1 MSC1210 DescriptionThe MicroSystem family of devices is designed for high-resolution measure-ment applications in smart tran

Input Multiplexer12-4The positive input channel and the negative input channel are selected in theADC Multiplexer register (ADMUX, SFR D7h). The high

Temperature Sensor12-5Analog-to-Digital Converter12.3 Temperature SensorAs shown in the chart above describing the ADMUX SFR, when all bits are setto

Temperature Sensor12-6ADCON3 =(decimation>>8) & 0x07; // MSB of decimationADCON1 = 0x01; // bipolar, auto, self calibration, offset, gainpri

Burnout Current Sources12-7Analog-to-Digital Converter12.4 Burnout Current SourcesWhen the Burnout bit (BOD) is set in the ADC control register (ADCON

Input Buffer12-8The previous code detects either an open- or short-circuit situation based onthe ADC sample. Also note that the comparison is less tha

Programmable Gain Amplifier (PGA)12-9Analog-to-Digital Converter12.7 Programmable Gain Amplifier (PGA)The Programmable Gain Amplifier (PGA) can be set

Offset DAC12-1012.8 Offset DACThe input to the PGA can be shifted by half the full-scale input range of the PGAby using the Offset DAC (ODAC) register

Calibration12-11Analog-to-Digital Converter12.10 CalibrationThe offset and gain errors in the MSC1210 ADC, or a complete measurementsystem, can be red

Digital Filter12-1212.11 Digital FilterThe digital filter can use either the fast settling, sinc2, or sinc3 filter, as shownin Figure 12−4. In additio

Digital Filter12-13Analog-to-Digital ConverterFigure 12−5. Filter Frequency Responses

MSC1210 Pin-Out1-3Introduction to the MSC1210The on-chip FLASH memory is programmable in a variety of modes over awide temperature and operating volta

Digital Filter12-1412.11.1 Multiplexing ChannelsWhen the input changes suddenly, it will take a certain amount of time for theoutput to correctly repr

Voltage Reference12-15Analog-to-Digital ConverterNotice that the speed difference for the synchronized channel changes areonly different by a factor o

Summation/Shifter Register12-1612.13 Summation/Shifter RegisterThe MSC1210 includes a summation/shifter register that facilitates and in-creases the e

Summation/Shifter Register12-17Analog-to-Digital ConverterSSCON1 and SSCON0 (SSCON.7 and SSCON.6, respectively) control whichof the four modes the sum

Summation/Shifter Register12-1812.13.1 Manual Summation ModeThe first mode of operation, manual summation, allows you to quickly add32-bit values. In

Summation/Shifter Register12-19Analog-to-Digital Converter12.13.3 Manual Shift (Divide) ModeThe manual shift/divide mode provides a quick method of di

Interrupt-Driven ADC Sampling12-2012.14 Interrupt-Driven ADC SamplingA useful, power-saving technique for obtaining ADC samples includes usingthe powe

Interrupt-Driven ADC Sampling12-21Analog-to-Digital ConverterADCON2 = decimation & 0xFF; // LSB of decimationADCON3 =(decimation>>8) & 0

Syncronizing Multiple MSC1210 Devices12-2212.15 Syncronizing Multiple MSC1210 DevicesIn some circumstances, it may be desirable to have data conversio

Syncronizing Multiple MSC1210 Devices12-23Analog-to-Digital Converter#include <REG1210.H>#include <stdio.h>#include <stdlib.h>#inclu

MSC1210 Pin-Out1-4Table 1−1.Pin Descriptions of the MSC1210Pin # Name Description1 XOUT The crystal oscillator pin XOUT supports parallel resonant AT

Ratiometric Measurements12-2412.16 Ratiometric MeasurementsRatiometric measurements may be used to eliminate potential inaccuracyfrom the ADC process.

Ratiometric Measurements12-25Analog-to-Digital Converter12.16.1 Differential VREFOne application would be a system where the measurement and the ADC a

12-26

13-1Serial Peripheral Interface (SPI)  $ , $!Chapter 13 describes the serial peripheral interface (SPI) of the MSC1210ADC

Description13-213.1 DescriptionThe MSC1210 includes a serial peripheral interface (SPI) module that allowssimple and efficient access to SPI-compatibl

Functional Description13-3Serial Peripheral Interface (SPI)Figure 13−2. SPI Clock/Data TimingDuring an SPI transfer, data is simultaneously transmitte

Clock Phase and Polarity Controls13-413.3 Clock Phase and Polarity ControlsSoftware can select one of four combinations of serial clock phase and pola

SPI Signals13-5Serial Peripheral Interface (SPI)13.4 SPI SignalsThe following paragraphs contain descriptions of the four SPI signals: masterin slave

SPI System Errors13-613.5 SPI System ErrorsSome SPI systems define two types of system errors: write collision and modefault. Write collision is defin

Data Transfers13-7Serial Peripheral Interface (SPI)13.6 Data TransfersThe transmitted and received data for SPI transfers are both double-buffered.Thi

MSC1210 Pin-Out1-5Introduction to the MSC1210Table 1−1 Pin Descriptions of the MSC1210 (Continued)Pin # Name Description34-40, 43 P2.0-P2.7 Port 2 is

Data Transfers13-8The SPI Receive control register, SPIRCON (9CH), controls the data receiveoperation. The receive buffer can be flushed with the writ

FIFO Operation13-9Serial Peripheral Interface (SPI)13.7 FIFO OperationData transmitted by the SPI interface is written to the SPIDATA register. If the

Code Examples13-1013.8 Code Examples13.8.1 SPI Master Transfer in Double-Buffer Mode using Interrupt PollingExample 13−1. SPI Master Transfer in Doubl

SPI Master Transfer in FIFO Mode using Interrupts13-11Serial Peripheral Interface (SPI)13.8.2 SPI Master Transfer in FIFO Mode using InterruptsExample

SPI Master Transfer in FIFO Mode using Interrupts13-12Line 11 enables the SPIRX and SPITX interrupts, after which the AI flag iscleared and the EAI fl

14-1Additional MSC1210 Hardware #  -%Chapter 14 describes addtional hardware on the MSC1210 ADC.Topic Page14.1 Description 14-

Description14-214.1 DescriptionThe MSC1210 includes a number of special hardware features above andbeyond those of a typical MCS−51 part.14.2 Low-Volt

Low-Voltage Detect14-3Additional MSC1210 HardwareThe detect circuit must activate whenever the supply voltage drops below theprogrammed level. In orde

Watchdog Timer14-414.3 Watchdog TimerThe watchdog timer is used to ensure that the CPU is executing the userprogram and not some random sequence of in

Watchdog Timer14-5Additional MSC1210 HardwareNote:The HCR0 and HCR1 registers may be set by the TI downloader applicationat download time. It may also

MSC1210 Pin-Out1-6Table 1−1 Pin Descriptions of the MSC1210 (Continued)Pin # Name Description46, 47,49-54P0.0−P0.7 P0.5 AD5 Address/Data Bit 549-54P0.

Watchdog Timer14-6Although the watchdog timeout value (0x07 in the previous example) may beset at the same time as the EWDT bit is cleared, it may be

Watchdog Timer14-7Additional MSC1210 Hardware14.3.3 Resetting the Watchdog TimerYour program, when operating properly, must reset the watchdog periodi

Watchdog Timer14-814.3.4 Disabling Watchdog TimerOnce the watchdog timer is activated, it operates continuously and your pro-gram must reset the watch

15-1Advanced Topics #+ Chapter 15 describes advanced topics associated with the MSC1210 ADC.Topic Page15.1 Hardware Configuration 15-2. .

Hardware Configuration15-215.1 Hardware ConfigurationIn addition to whatever amount of flash memory the specific MSC1210 partcontains (which may be pa

Hardware Configuration15-3Advanced Topics15.1.1.1 Hardware Configuration Register 0 (HCR0)Hardware configuration register 0 (HCR0) is used to configur

Hardware Configuration15-415.1.1.2 Hardware Configuration Register 1 (HCR1)Hardware configuration register 1 (HCR1) is used primarily to configure the

Hardware Configuration15-5Advanced Topics15.1.2 Hardware Configuration MemoryIn addition to the hardware configuration registers, 116 bytes of configu

Advanced Flash Memory15-615.2 Advanced Flash MemoryFlash memory may be configured as data memory, program memory, or both.15.2.1 Write Protecting Flas

Breakpoint Generator15-7Advanced Topics15.3 Breakpoint GeneratorThe purpose of the breakpoint block is to generate an interrupt whenever thedesired pr

MSC1210 Pin-Out1-7Introduction to the MSC12101.2.1.2 Port 1Port 1 consists of eight I/O lines that may be used to interface to external parts.Port 1 i

Breakpoint Generator15-8To configure a breakpoint, the following steps should be taken:1) The BPSEL (MCON.7) bit must be set to either 0 (for Breakpoi

Power Optimization15-9Advanced Topics15.4 Power OptimizationThe MSC1210, like a standard 8052, has the ability to operate in apower-saving mode, known

Flash Memory as Data Memory15-1015.5 Flash Memory as Data MemoryIf so configured in HCR0, some portion of flash memory can be accessed byyour applicat

Flash Memory as Data Memory15-11Advanced Topicsunsigned char i;// synchronize baud rateautobaud();// Set the pointer to the beginning of the page to m

Advanced Topics and Other Information15-1215.6 Advanced Topics and Other Information15.6.1 Serial and Parallel Programming of the MSC1210The MSC1210 f

16-18052 Assembly Language ./0#01Chapter 16 describes the 8052 Assembly Language.Topic PageChapter 1616.1 Description 16-2. . . . . .

Description16-216.1 DescriptionAssembly language is a low-level, pseudo-English representation of the mi-crocontroller’s machine language. Each assemb

Syntax16-38052 Assembly LanguageIn summary, a typical 8052 assembly language line might appear as:MYLABEL: MOV A,#25h ;This is just a sample commentIn

Number Bases16-416.3 Number BasesMost assemblers are capable of accepting numeric data in a variety of numberbases. Commonly supported are decimal, he

Operator Precedence16-58052 Assembly Language16.5 Operator PrecedenceMathematical operators within an expression are subject to the following orderof

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvemen

MSC1210 Pin-Out1-81.2.1.3 Port 2Like port 0, port 2 is dual-function. In some circuit designs, it is available for access-ing external devices, while

Changing Program Flow (LJMP, SJMP, AJMP)16-616.7 Changing Program Flow (LJMP, SJMP, AJMP)LJMP, SJMP and AJMP are used as a go to in assembly language.

Subroutines (LCALL, ACALL, RET)16-78052 Assembly Language16.8 Subroutines (LCALL, ACALL, RET)As in other languages, 8052 assembly language permits the

Register Assignment (MOV)16-8Note:Recursive subroutines (subroutines that call themselves) are a very popularmethod of solving some common programming

Register Assignment (MOV)16-98052 Assembly LanguageAs already mentioned, the MOV instruction is one of the most common andvital instructions that an 8

Register Assignment (MOV)16-10With this knowledge of the MOV instruction, some simple memory assignmenttasks can be performed:1) Clear the contents of

Incrementing and Decrementing Registers (INC, DEC)16-118052 Assembly Language16.10 Incrementing and Decrementing Registers (INC, DEC)Two instructions,

Program Loops (DJNZ)16-1216.11 Program Loops (DJNZ)Many operations are conducted within finite loops. That is, a given code seg-ment is executed repea

Setting, Clearing, and Moving Bits (SETB, CLR, CPL, MOV)16-138052 Assembly Language16.12 Setting, Clearing, and Moving Bits (SETB, CLR, CPL, MOV)One v

Setting, Clearing, and Moving Bits (SETB, CLR, CPL, MOV)16-14Finally, the SETB TR1 example shows a typical use of SETB to set an individu-al bit of an

Bit-Based Decisions and Branching (JB, JBC, JNB, JC, JNC)16-158052 Assembly Language16.13 Bit-Based Decisions and Branching (JB, JBC, JNB, JC, JNC)It

MSC1210 Pin-Out1-9Introduction to the MSC1210P3.2 (INT0): When so configured, this line is used to trigger an external 0 Inter-rupt. This may either b

Value Comparison (CJNE)16-1616.14 Value Comparison (CJNE)CJNE (compare, jump if not equal) is a very important instruction. It is used tocompare the v

Less Than and Greater Than Comparison (CJNE)16-178052 Assembly LanguageCode structures similar to the one shown previously are very common in 8052asse

Zero and Non-Zero Decisions (JZ/JNZ)16-1816.16 Zero and Non-Zero Decisions (JZ/JNZ)Sometimes, it is useful to be able to simply determine if the accum

Performing Additions (ADD, ADDC)16-198052 Assembly LanguageThis code assumes that a 16-bit number is in Internal RAM address 30H (highbyte) and addres

Performing Subtractions (SUBB)16-2016.18 Performing Subtractions (SUBB)The SUBB instruction provides a way to perform 8-bit subtraction. All subtrac-t

Performing Multiplication (MUL)16-218052 Assembly Language16.19 Performing Multiplication (MUL)In addition to addition and subtraction, the 8052 also

Performing Division (DIV)16-2216.20 Performing Division (DIV)The last of the basic mathematics functions offered by the 8052 is the DIV ABinstruction.

Shifting Bits (RR, RRC, RL, RLC)16-238052 Assembly Language16.21 Shifting Bits (RR, RRC, RL, RLC)The 8052 offers four instructions that are used to sh

Bit-Wise Logical Instructions (ANL, ORL, XRL)16-2416.22 Bit-Wise Logical Instructions (ANL, ORL, XRL)The 8052 instruction set offers three instruction

Bit-Wise Logical Instructions (ANL, ORL, XRL)16-258052 Assembly LanguageMost of the logical bit-wise instructions affect entire 8-bit memory registers

MSC1210 Pin-Out1-101.2.3 Reset Line (RST)Pin 13 is the master reset line for the microcontroller. When this pin is broughthigh for two instruction cyc

Exchanging Register Values (XCH)16-2616.23 Exchanging Register Values (XCH)Very often, the value of the accumulator will need to be swapped with the v

Adjusting Accumulator for BCD Addition (DA)16-278052 Assembly Language16.26 Adjusting Accumulator for BCD Addition (DA)DA A is a very useful instructi

Using the Stack (PUSH/POP)16-2816.27 Using the Stack (PUSH/POP)The stack, as with any processor, is an area of memory that can be used to storeinforma

Using the Stack (PUSH/POP)16-298052 Assembly LanguageThe stack itself resides in internal RAM and is managed by the SP (stack point-er) SFR. SP will a

Setting the Data Pointer DPTR (MOV DPTR)16-3016.28 Setting the Data Pointer DPTR (MOV DPTR)The next few instructions use the data pointer (DPTR), the

Reading and Writing External RAM/Data Memory (MOVX)16-318052 Assembly Language16.29 Reading and Writing External RAM/Data Memory (MOVX)The 8052 genera

Reading Code Memory/Tables (MOVC)16-3216.30 Reading Code Memory/Tables (MOVC)It is often useful to be able to read code memory itself from within a pr

Reading Code Memory/Tables (MOVC)16-338052 Assembly LanguageFor example, if the data in the previous example are located right after the rou-tine that

Using Jump Tables (JMP @A+DPTR)16-3416.31 Using Jump Tables (JMP @A+DPTR)A frequent method for quickly branching to many different areas in a programi

17-1Keil Simulator 2 Chapter 17 describes the Keil simulator and its functions.Topic Page17.1 Description 17-2. . . . . . . . . . . . . .

MSC1210 Pin-Out1-11Introduction to the MSC12101.2.6 External Access (EA)The external access (EA) line at pin 48 is used to determine whether theMSC121

Description17-217.1 DescriptionThe µVision2 is an integrated software development platform that combines a ro-bust screen editor, and project manager

Description17-3Keil Simulator3) There are also some labeled check boxes whose statuses, checked orcleared, directly affect the associated bit within t

Timers17-417.2 TimersThe simulator peripheral timer has three timer/counter modules: Timers 0, 1,and 2; a system timer module; and a watchdog module.

Timers17-5Keil SimulatorDue to the MSC1210 peripherals being modular and relatively independent, evenif they share registers, each peripheral has it o

Timers17-6Figure 17−4. Timer/Counter 1 Mode 1Figure 17−5. Interrupt System

Timers17-7Keil SimulatorThe following is a listing of the C code used to demonstrate the timing and inter-rupting features of Timer/Counters 0 and 1.T

Timers17-8void interrupt_timer0 ( ) interrupt 1 using 1{ /*This ISR is called when a type 1 interrupt causes the processor to vectorinto the code segm

Timers17-9Keil SimulatorEvery time the idle loop is interrupted, the MSC1210 vectors to the ISR of theinterrupting signal. If the interrupt source is

Timers17-10end_test = 0;//Timer 0 TH0:TL0 will always count up from 0x0200 until overflow,//and will be replenished with 0x0200 indefinitelycount_star

Timer 217-11Keil Simulator17.3 Timer 2Timer/Counter 2 is quite different from the two other timers. The operationmode is determined by the status of o

Enhanced 8051 Core1-121.3 Enhanced 8051 CoreThe MSC1210 is an 8052-based family of high-performance, mixed-signalcontrollers. All instructions in the

Watchdog Timer17-1217.4 Watchdog TimerThe process of setting, and the operation of the watchdog timer peripheral fa-cility are similar to those of the

Watchdog Timer17-13Keil SimulatorThe non-editable Expire in: display window indicates the amount of time left (inmilliseconds) before you must perform

Watchdog Timer17-14/*//For the actual device, the a logical AND of the content of the FRC0 SFRregister with 0xF7 must be performed to Disable the Watc

Watchdog Timer17-15Keil Simulator/*start short loop to test DWDT*/for (i = 0; i < 4000; i ++){//idle delayj = (i *13) % 4000;}//Disable watchdog ti

System Timer17-1617.5 System TimerThe MSC1210 device has many time ticks and an additional clock generator(1MHz) that are derived, and, therefore, syn

Analog-to-Digital Converter17-17Keil Simulator17.7 Analog-to-Digital ConverterData entry and bit pattern setting facilities for the ADC peripheral are

Analog-to-Digital Converter17-18Figure 17−8. Analog−to−Digital Converter PeripheralFor each analog input source whose editable text windows are displa

Analog-to-Digital Converter17-19Keil SimulatorSIGNAL void a_to_d_sim (void){inti;/*Data written into the variable ain0 is automaticallyentered into th

Summation/Shifter17-2017.8 Summation/ShifterThe summation/shifter module implemented in this simulator package allowsthe developer to experience how t

Summation/Shifter17-21Keil SimulatorThe non-editable text window across from the acc count shows the currentnumber of data samples accumulated into th

Family Device Compatibility1-13Introduction to the MSC12101.4 Family Device CompatibilityThe hardware functionality and pin outs across the MSC1210 fa

Summation/Shifter17-22This setting essentially causes the 32-bit accumulator to collect eight consecu-tive data samples from the ADC. Upon completion,

Summation/Shifter17-23Keil Simulatorto a LONG integer*/long j;j = ACR3;j <<= 8;j += ACR2;j <<= 8;j += ACR1;j <<= 8;j += ACR0;return

Summation/Shifter17-24while(!(AISTAT & 0x20));j = ADRESL;for (i = 0; i < 20; i++){ // dump 20 conversions/*wait for DRBY bit*/while(!(AISTAT &a

Summation/Shifter17-25Keil Simulatorchar accum_count;long l;float voltage_value, vref, max_range;char convert_accumulate;convert_accumulate = 1; //Sel

Summation/Shifter17-26}switch (convert_accumulate){case CONVERT: //straight A/D conversion results, no averagingPAI = 0x20;for (i = 0; i < 0x40; i+

Summation/Shifter17-27Keil SimulatorIn order to demonstrate how the summation/shifter handles the incrementalaccumulation of sampled data, we have opt

Summation/Shifter17-28Figure 17−11.summation/Shifter PeripheralFigure 17−12. The ADC Peripheral Mid-Stride a Typical 8-Sample Averaging Block

Summation/Shifter17-29Keil SimulatorIn addition to the previous sample code, a sample driving code for the debuggingis included below. This is a speci

Interrupts17-3017.9 InterruptsThe list box for the interrupt peripheral is shown in Figure 17−13. The figureshows a list of interrupt sources along wi

Ports17-31Keil Simulator17.10 PortsThere are four parallel I/O ports on this device, Port 0, Port 1, Port 2 and Port3, and as such, there are four sep

High-Performance Peripherals1-141.7 High-Performance PeripheralsHigh-performance peripherals are included on-chip, which offload CPU proc-essing and c

Serial Peripheral Interface (SPI)17-3217.11 Serial Peripheral Interface (SPI)The serial peripheral interface (SPI) implemented in this simulator packa

Serial Peripheral Interface (SPI)17-33Keil Simulatordata displayed in the SPICON window, on the basis of the bit position of thecorresponding configur

Serial Peripheral Interface (SPI)17-34and the TXIRQ window determine the check/clear status of the SPIT checkbox. As data is being received from the e

Serial Peripheral Interface (SPI)17-35Keil Simulator#include ”MSC1210.H”//unsigned char data irqen_init _at_ 0x7f ; // image of PAI#define FWVer 0x04#

Serial Peripheral Interface (SPI)17-36SPIEND = 0x0b0;/*Master mode: set MISO for input, and MOSI, SS & SCK for strong outputs*/P1DDRH = 0x75;P1 |=

Serial Peripheral Interface (SPI)17-37Keil Simulatorif (AISTAT & 0x04){/*Receiver*/i = SPIRCON & 0x7F; //extract the count for the number ofAI

mVision 2 Debug Program Example17-3817.12 µVision 2 Debug Program ExampleSIGNAL void spi_sim (void){/*This program runs in parallel with the main prog

mVision 2 Debug Program Example17-39Keil SimulatorFigure 17−17. Keil DebuggerThe window labeled Serial #1 shows the printed ASCII character representa

Serial Port I/O17-4017.13 Serial Port I/OIn addition to the SPI communication protocol that was presented earlier in thismanual, the more basic serial

Serial Port I/O17-41Keil SimulatorA snapshot of the Serial Channel 0 communication peripheral after at typicalshow_baud_gen ( ) subroutines execution

2-1MSC1210 Memory Organization   This chapter defines the Memory Organization of MSC1210 ADC.Topic Page2.1 Description 2-2.

Serial Port I/O17-4217.13.1 Serial Port 0 Operation Mode 1 Examplevoid show_baud_gen (void){ P3DDRL &= 0xf0; P3DDRL |= 0x07; //P30 input, P31 ou

Serial Port I/O17-43Keil Simulator17.13.2 Transmit Block Baud Rate ComputationIn this example, two different baud rate sources have been used, one for

Serial Port I/O17-4417.13.3 Receive Block Baud Rate ComputationTimer 1 is set for a mode 2 timer operation in an 8-bit auto-reload capacity. Thisis ac

Serial Port I/O17-45Keil SimulatorFigure 17−19. Clock Control PeripheralFigure 17−20. USART0 Preipheral

Additional Resource17-4617.14 Additional ResourceIt is highly recommended that you review the Keil Compiler tutorial integratedinto this package for a

A-1Additional Features in the MSC1210 Compared to the 8052#0000000./Appendix A deals with additional featu

Additional Features in the MSC1210 Compared to 8052A-2A.1 Additional Features in the MSC1210 Compared to 8052The MSC1210 includes the following featur

B-1Clock Timing Diagram300*Appendix B diagrams the MSC1210 ADC timing chain and clock control.Topic PageB.1 MSC1210 Timing Chain and C

MSC1210 Timing Chain and Clock Control DiagramB-2B.1 MSC1210 Timing Chain and Clock Control DiagramFigure B−1.MSC1210 Timing Chain and Clock Control

C-1Boot ROM Routines"00Appendix C defines the MSC1210 ADC boot ROM routines.Topic PageC.1 Description C-2. . . . . . . . . . . . .

Description2-22.1 DescriptionThe MCS1210 has three very general types of memory. To program theMCS1210 effectively, it is necessary to have a basic un

DescriptionC-2C.1 DescriptionThe MSC1210 has a 2K ROM. This code provides the interaction for serial andparallel programming. There are also several r

DescriptionC-3Boot ROM RoutinesC parameters are passed to the subroutine code such that the first parameteris passed in R7, whereas additional paramet

C-4

D-18052 Instruction-Set Quick-Reference Guide./0)043),0(Appendix D gives a list of the 8052 instruction set.Topic PageD

8052 Instruction-Set Quick-Reference GuideD-2D.1 8052 Instruction-Set Quick-Reference Guide00 NOP 40 JC relAddr 80 SJMP relAddr C0 PUSH direct01 AJMP

E-18052 Instruction Set./00Appendix E lists the 8052 instruction set.Topic PageE.1 Description E-2. . . . . . . . . . . . . . . . . .

DescriptionE-2E.1 DescriptionThis appendix is a reference for all instructions in the 8052 instruction set. Foreach instruction, the following informa

8052 Instruction SetE-38052 Instruction SetE.2 8052 Instruction SetACALL Absolute Call within 2k BlockSyntax ACALL codeAddressInstructions OpCode Byte

8052 Instruction SetE-4ADD, ADDC Add Value, Add Value with CarrySyntax ADD A,operandADDC A,operandInstructions OpCode Bytes Cycles FlagsADD A,#data8 0

8052 Instruction SetE-58052 Instruction SetThe auxillary carry (AC) bit is set if there is a carry-out of bit 3. In other words,if the unsigned summed

Program Memory2-3MSC1210 Memory OrganizationFor example, in the Y5 model there is 32k flash memory available. This 32kmay be configured as either prog

8052 Instruction SetE-6ANL Bitwise ANDSyntax ANL operand1,operand2Instructions OpCode Bytes Cycles FlagsANL direct,A 0x52 2 1 NoneANL direct,#data8 0x

8052 Instruction SetE-78052 Instruction SetCJNE Compare and Jump if Not EqualSyntax CJNE operand1,operand2,reladdrInstructions OpCode Bytes Cycles Fla

8052 Instruction SetE-8CPL Complement RegisterSyntax CPL operandInstructions OpCode Bytes Cycles FlagsCPL A 0xF4 1 1 NoneCPL C 0xB3 1 1 CCPL bitAddr 0

8052 Instruction SetE-98052 Instruction SetDEC Decrement RegisterSyntax DEC registerInstructions OpCode Bytes Cycles FlagsDEC A 0x14 1 1 NoneDEC direc

8052 Instruction SetE-10DJNZ Decrement and Jump if Not ZeroSyntax DJNZ register,relAddrInstructions OpCode Bytes Cycles FlagsDJNZ direct,relAddr 0xD5

8052 Instruction SetE-118052 Instruction SetINC Increment ReisterSyntax INC registerInstructions OpCode Bytes Cycles FlagsINC A 0x04 1 1 NoneINC direc

8052 Instruction SetE-12JB Jump if Bit SetSyntax JB bitAddr,relAddrInstructions OpCode Bytes Cycles FlagsJB bitAddr,relAddr 0x20 3 2 NoneJB branches t

8052 Instruction SetE-138052 Instruction SetJMP Jump to Data Pointer + AccumulatorSyntax JMP @A+DPTRInstructions OpCode Bytes Cycles FlagsJMP @A+DPTR

8052 Instruction SetE-14JNZ Jump if Accumulator Not ZeroSyntax JNZ reladdrInstructions OpCode Bytes Cycles FlagsJNZ relAddr 0x70 2 2 NoneJNZ branches

8052 Instruction SetE-158052 Instruction SetMOV Move Memory Into/Out of AccumulatorSyntax MOV operand1, operand2Instructions OpCode Bytes Cycles Flags

Contentsi Contents1 Introduction to the MSC1210 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Memory2-4Table 2−2.Program and Data Memory Addresses.HCR0 MSC1210Y2 MSC1210Y3 MSC1210Y4 MSC1210Y5DFSEL PM DM PM DM PM DM PM DM000 (reserved) — —

8052 Instruction SetE-16MOV Move into/out of Internal RAMSyntax MOV operand1,operand2Instructions OpCode Bytes Cycles FlagsMOV @R0,#data8 0x76 2 1 Non

8052 Instruction SetE-178052 Instruction SetMOV DPTR Move value into DPTRSyntax MOV DPTR,#data16Instructions OpCode Bytes Cycles FlagsMOV DPTR,#data16

8052 Instruction SetE-18MUL Multiply Accumulator by BSyntax MUL ABInstructions OpCode Bytes Cycles FlagsMUL AB 0xA4 1 4 C, OVMUL multiplies the unsign

8052 Instruction SetE-198052 Instruction SetORL Bitwise ORSyntax Syntax: ORL operand1,operand2Instructions OpCode Bytes Cycles FlagsORL direct,A 0x42

8052 Instruction SetE-20POP Pop Value from StackSyntax POP registerInstructions OpCode Bytes Cycles FlagsPOP direct 0xD0 2 2 NonePOP pops the last val

8052 Instruction SetE-218052 Instruction SetRET Return from SubroutineSyntax RETInstructions OpCode Bytes Cycles FlagsRET 0x22 1 2 NoneRET is used to

8052 Instruction SetE-22RLC – Rotate Accumulator Left Through CarrySyntax RLC AInstructions OpCode Bytes Cycles FlagsRLC A 0x33 1 1 CRLC shifts the b

8052 Instruction SetE-238052 Instruction SetSJMP Short JumpSyntax SJMP relAddrInstructions OpCode Bytes Cycles FlagsSJMP relAddr 0x80 2 2 NoneSJMP jum

8052 Instruction SetE-24SWAP Subtract Accumulator NibblesSyntax SWAP AInstructions OpCode Bytes Cycles FlagsSWAP A 0xC4 1 1 NoneSWAP swaps bits 0−3 of

8052 Instruction SetE-258052 Instruction SetXRL Bitwise Exclusive ORSyntax XRL operand1,operand2Instructions OpCode Bytes Cycles FlagsXRL direct,A 0x6

Data Memory2-5MSC1210 Memory OrganizationOn-chip extended static RAM provides 1k of data memory that requires no ex-ternal circuitry and is available

8052 Instruction SetE-26UNDEFINED Undefined InstructionSyntax ???Instructions OpCode Bytes Cycles Flags??? 0xA5 1 1 CThe undefined instruction is, as

F-1Bit-Addressable SFRs (alphabetical)")#00!Appendix F defines the MSC1210 bit-addressable special function register

Bit Addressable SFRs (alphabetical)F-2F.1 Bit Addressable SFRs (alphabetical)Enable Interrupt Control (EICON)SFR Name: EICONSFR Address: D8HBit-Addres

Bit Addressable SFRs (alphabetical)F-3Bit-Addressable SFRs (alphabetical)Extended Interrupt Priority (EIP)SFR Name: EIESFR Address: F8HBit-Addressable

Bit Addressable SFRs (alphabetical)F-4INTERRUPT PRIORITY (IP)SFR Name: IPSFR Address: B8HBit−Addressable: YesBit−Definitions:bit 7 bit 6 bit 5 bit 4 b

Bit Addressable SFRs (alphabetical)F-5Bit-Addressable SFRs (alphabetical)Port 1 (P1)SFR Name: P1SFR Address: 90HBit−Addressable: YesBit−Definitions:bi

Bit Addressable SFRs (alphabetical)F-6Port 3 (P3)SFR Name: P3SFR Address: B0HBit−Addressable: YesBit−Definitions:bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 b

Bit Addressable SFRs (alphabetical)F-7Bit-Addressable SFRs (alphabetical)Program Status Word (PSW)SFR Name: PSWSFR Address: D0HBit−Addressable: YesBit

Bit Addressable SFRs (alphabetical)F-8Serial Control (SCON)SFR Name: SCONSFR Address: 98HBit−Addressable: YesBit−Definitions:bit 7 bit 6 bit 5 bit 4 b

Bit Addressable SFRs (alphabetical)F-9Bit-Addressable SFRs (alphabetical)Timer Control (TCON)SFR Name: TCONSFR Address: 88HBit−Addressable: YesBit−Def

Internal RAM2-6Figure 2−2. MSC1210 Memory Map Register Bank.2.4 Internal RAMAs shown in Figure 2−2, the MSC1210 has a bank of 256 bytes of internalRAM

Bit Addressable SFRs (alphabetical)F-10Timer 2 Control (T2CON)SFR Name: T2CONSFR Address: C8HBit−Addressable: YesBit−Definitions:bit 7 bit 6 bit 5 bi

G-1SFRs/Address Cross-Reference Guide (alphabetical)'#0),0(!Appendix G lists an alphabetical cross-refere

SFR/Address Cross-ReferenceG-2G.1 SFR/Address Cross-ReferenceSFR Name Description SFR Address (Hex)ACLK Analog Clock F6HADCON0 ADC Control 0 DCHADCON1

SFR/Address Cross-ReferenceG-3SFRs/Address Cross-Reference Guide (alphabetical)MPAGEMemory Page 92HMSECH Millisecond Counter High FDHMSECL Millisecond

SFR/Address Cross-ReferenceG-4SPIRCONSPI Receive Control 9CHSPISTART SPI Buffer Start Address 9EHSPITCON SPI Transmit Control 9DHSRST System Reset F7H

Internal RAM2-7MSC1210 Memory Organization2.4.1 The StackThe stack is a “last in, first out” (LIFO) storage area that exists in internal RAM.It is use

Internal RAM2-8But watch out! As the memory map shows, the MSC1210 has four distinct registerbanks. When the MSC1210 is first reset, register bank 0 (

Internal RAM2-9MSC1210 Memory OrganizationAs shown, bit memory is not really a new type of memory, it is just a subset ofinternal RAM. However, becaus

Internal RAM2-102.4.4 Special Function Register (SFR) MemorySFRs are areas of memory that control specific functionality of the MSC1210.For example, f

3-1Special Function Registers (SFRs)    !Chapter 3 defines the MSC1210 SFRs.Topic Page3.1 Description 3-2. . . . . . .

Description3-23.1 DescriptionThe MSC1210 is a flexible microcontroller with a relatively large number ofmodes of operation. Your program may inspect a

Referencing SFRs3-3Special Function Registers (SFRs)3.2 Referencing SFRsWhen writing code in assembly language, SFRs may be referenced either bytheir

Contentsii5 Addressing Modes 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bit−Addressable SFRs3-43.3 Bit−Addressable SFRsAll SFRs that have addresses divisible by eight (i.e., 80H, 88H, 90H, 98H, etc.)are bit-addressable. Th

SFR Definitions3-5Special Function Registers (SFRs)3.5 SFR DefinitionsThis section will endeavor to quickly overview each of the SFRs found in theSFR

SFR Definitions3-6DPL0/DPH0 (Data Pointer 0 Low/High, Addresses 82H/83H): The SFRsDPL0 and DPH0 work together to represent a 16-bit value called Data

SFR Definitions3-7Special Function Registers (SFRs)TMOD (Timer Mode, Address 89H): This SFR is used to configure the modeof operation of each of the t

SFR Definitions3-8MPAGE (Memory Page, Address 92H): This SFR contains the high byte ofthe address to access when using the MOVX @Ri instructions. A no

SFR Definitions3-9Special Function Registers (SFRs)SPIRCON (SPI Receive Control, Address 9CH): This SFR is dual-purpose:when read, it will return the

SFR Definitions3-10AISTAT (Auxiliary Interrupt Status, Address A7H): This is a read-only SFRthat will provide you with the current status of all the e

SFR Definitions3-11Special Function Registers (SFRs)SCON1 (Serial Control 1, Address C0H, Bit-Addressable): This SFR isused to configure the behavior

SFR Definitions3-12ADCON0/ADCON1 (ADC Control 0 and 1, Addresses DCH/DDH): Thesetwo SFRs allow the user program to configure various aspects of the AD

SFR Definitions3-13Special Function Registers (SFRs)FTCON (Flash Memory Timing Control, Address EFH): This SFR controlsthe timing and period of flash

Contentsiii Contents10 Interrupts 10-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SFR Definitions3-14MSINT (Milliseconds Interrupt, Address FAH): This SFR can be set tocause an interrupt to occur after the specified number of millis

4-1Basic Registers " Chapter 4 describes the basic register functions of the MSC1210 ADC.Topic Page4.1 Description 4-2. . . . . . .

Description4-24.1 DescriptionA number of MSC1210 registers can be considered basic. Very little can bedone without them and a detailed explanation of

B Register4-3Basic RegistersAs mentioned previously, there are four sets of R registers: register bank 0, 1,2, and 3. When the MSC1210 is first powere

Data Pointer (DPTR0/DPTR1)4-44.6 Data Pointer (DPTR0/DPTR1)The data pointer (DPTR0/DPTR1) is the user-accessible 16-bit (2-byte) regis-ter of the MSC1

5-1Addressing Modes # Chapter 5 describes the various addressing modes of the MSC1210.Topic Page5.1 Description 5-2. . . . . . . . . .

Description5-25.1 DescriptionAs is the case with all microcomputers from the PDP-8 onwards, the MSC1210uses several memory addressing modes. An addres

Direct Addressing5-3Addressing Modes5.3 Direct AddressingDirect addressing is so named because the value to be stored in memory isobtained by directly

Indirect Addressing5-45.4 Indirect AddressingIndirect addressing is a very powerful addressing mode that in many casesprovides an exceptional level of

External Direct Addressing5-5Addressing Modes5.5 External Direct AddressingExternal memory is accessed using a suite of instructions that use external

Contentsiv13 Serial Peripheral Interface (SPI) 13-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Indirect Addressing5-65.6 External Indirect AddressingExternal memory can also be accessed using a form of indirect addressingcalled external

6-1Program Flow $ %Chapter 6 describes the program flow of the MSC1210 ADC.Topic Page6.1 Description 6-2. . . . . . . . . . . . . . . . . .

Description6-26.1 DescriptionWhen the MSC1210 is first initialized the PC SFR is cleared to 0000H. The partthen begins to execute instructions sequent

Direct Jumps6-3Program FlowConsider the example:LJMP NEW_ADDRESS...NEW_ADDRESS: ...The LJMP instruction in this example means “Long Jump.” When theMS

Direct Calls6-46.4 Direct CallsAnother operation that will be familiar to seasoned programmers is the LCALLinstruction. This is similar to a “GOSUB” c

7-1System Timing  Chapter 7 describes the system timing of the MSC1210 ADC.Topic Page7.1 Description 7-2. . . . . . . . . . . . . . . . .

Description7-27.1 DescriptionIn order to understand—and better make use of—the MSC1210, it is neces-sary to understand some underlying information con

Description7-3System TimingAn instruction cycle is, in reality, four clock cycles. That is to say, if an instruc-tion takes one instruction cycle to e

System Timers7-47.2 System TimersIn addition to the standard 8052 timers to be described in Chapter 8, theMSC1210 includes the following system timers

System Timers7-5System TimingFigure 7−2. MSC1210 Timing Chain and Clock ControlFigure 7−3. SPI/PWM/Flash Write Timing

Contentsv Contents16 8052 Assembly Language 16-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Timers7-67.2.1 Microseconds TimerThe microseconds timer is used by the MSC1210 in order to establish a 1µsclock. This clock, in turn, is used b

System Timers7-7System TimingFigure 7−4. System Timing Interrupt ControlThe MSECH (FDH) and MSECL (FCH) SFRs should be set to a value such thatthe sy

System Timers7-87.2.2.2 One Hundred Millisecond ClockThe one hundred millisecond clock is used by the MSC1210 in order to estab-lish a 10Hz clock. Thi

Startup Timing7-9System Timing7.3 Startup TimingWhen power is turned on, or a reset is initiated, a power-on delay circuit is im-plemented with a 17-b

Startup Timing7-10Figure 7−7. Serial Flash Programming Power-On Timing (EA is ignored)Table 7−1.Signal Definitions for Reset Timing DiagramsSymbol Par

8-1Timers Chapter 8 describes the timers of the MSC1210 ADC.Topic Page8.1 Description 8-2. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Description8-28.1 DescriptionThe MSC1210 comes equipped with three standard timer/counters, all ofwhich may be controlled, set, read, and configured i

Using Timers to Measure Time8-3TimersThe individual bits of TMOD have the following functions:7 6 5 4 3 2 1 0 Reset ValueSFR 8EH0 0 T2M T1M T0M MD2 MD

Using Timers to Measure Time8-4Unlike instructions—some of which require one instruction cycle, others 2, andothers 4—the timers are consistent. They

Using Timers to Measure Time8-5TimersIt is apparent that the maximum value a timer may have is 65,535 because thereare only two bytes devoted to the v

ContentsviA Additional Features in the MSC1210 Compared to the 8052 A-1. . . . . . . . . . . . . . . . . . . . . . . . . A.1 Additional Features in th

Using Timers to Measure Time8-6As is shown in the previous chart, four bits (two for each timer) are used tospecify a mode of operation. The modes of

Using Timers to Measure Time8-7TimersWhen the timer is in 13-bit mode, TLx will count from 0 to 31. When TLx is in-cremented from 31, it will roll ove

Using Timers to Measure Time8-8As shown, the value of TH0 never changed. In fact, when mode 2 is used, THxis almost always set to a known value and TL

Using Timers to Measure Time8-9TimersSo far, only four of the eight bits have been defined. That is because the otherfour bits of the SFR do not have

Using Timers to Measure Time8-10However, when dealing with a 13-bit or 16-bit timer, the chore is a little morecomplicated. Consider what happens when

Using Timers to Measure Time8-11TimersThis approach can be used to cause the program to execute a fixed delay. Asshown earlier, we calculated that it

Using Timers as Event Counters8-128.4 Using Timers as Event CountersWe have discussed how a timer can be used for the obvious purpose of keep-ing trac

Using Timer 28-13TimersIt is important to note that the MSC1210 checks the P3.4 line each instructioncycle (4 clock cycles). This means that if P3.4 i

Using Timer 28-14TR2 (bit 2)—Timer 1 Run Control. This bit enables/disables the operation ofTimer 2. Halting this timer will preserve the current coun

Using Timer 28-15Timers8.5.3 Timer 2 in Capture ModeA new mode, specific to Timer 2, is called capture mode. As the name implies,this mode captures th

Contentsvii Contents1−1. MSC1210 Block Diagram 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Using Timer 28-168.5.4 Timer 2 as a Baud Rate GeneratorTimer 2 can be used as a baud rate generator. This is accomplished by settingeither RCLK (T2CON

9-1Serial Communication  Chapter 9 describes serial communication using the MSC1210 ADC.Topic Page9.1 Description 9-2. . . . . . .

Description9-29.1 DescriptionThe MSC1210 family has three serial port interfaces: two UARTs and one SPI.This chapter will cover the UARTs, while the S

Setting the Serial Port Mode9-3Serial Communication9.2 Setting the Serial Port ModeThe first thing to be done when using the MSC1210 integrated serial

Setting the Serial Port Mode9-4TI_0 (bit 1)—Transmitter Interrupt Flag. This bit indicates that data in the Se-rial Port 0 buffer has been completely

Setting the Serial Port Mode9-5Serial CommunicationThe high four bits (bits 4 through 7) are configuration bits.The bit REN means receiver enable. Thi

Setting the Serial Port Mode9-6Figure 9−1. Serial Port 0 Mode 0 Transmit Timing—High Speed Operation.Figure 9−2. Serial Port Mode 0 Receive Timing—Hig

Setting the Serial Port Mode9-7Serial CommunicationFigure 9−3. Serial Port Mode 1 Transmit Timing.Figure 9−4. Serial Port 0 Mode 1 Receive Timing.Rece

Setting the Serial Port Mode9-8The baud rate is adjustable and is based on either Timer 1 or Timer 2. Serial Port0 can use either Timer 1 or Timer 2,

Setting the Serial Port Mode9-9Serial CommunicationThe divide-by-32 is a result of the fOSC being divided by 2 (by settingT2CON.TCLK and T2CON.RCLK) a