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R_SETUP w
t
CLR
(m)
t
cyc
* 1
R_STROBE w max
ǒ
ǒ
t
REA
(m) ) t
SU
Ǔ
t
cyc
,
t
RP
(m)
t
cyc
Ǔ
* 1
R_SETUP ) R_STROBE w
ǒ
t
CEA
(m) ) t
SU
Ǔ
t
cyc
* 1
R_HOLD w
ǒ
t
H
* t
CHZ
(m)
Ǔ
t
cyc
* 1
R_SETUP ) R_STROBE ) R_HOLD w
t
RC
(m)
t
cyc
* 3
TA w max
ǒ
t
CHZ
(m)
t
cyc
,
t
RHZ
(m) * (R_HOLD ) 1)t
cyc
t
cyc
Ǔ
* 1
Setup
Strobe
Hold
t
RC
(m)
t
RP
(m)
t
REA
(m)
t
CEA
(m)
t
SU
t
RHZ
(m)
t
H
t
CHZ
(m)
EM_CS
ALE_EM_A[1]
CLE_EM_A[2]
EM_OE
EM_D[7:0]
t
CLR
(m)
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Use Cases
From Figure 16, the following equations may be derived. t
cyc
is the period at which the EMIF operates. The
R_SETUP, R_STROBE, and R_HOLD fields are programmed in terms of EMIF cycles where as the data
sheet specifications are typically given is nano seconds. This is explains the presence of t
cyc
in the
denominator of the following equations. A minus 1 is included in the equations because each field in
ACFGn is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, R_SETUP is equal to
R_SETUP width in EMIF clock cycles minus 1 cycle.
The EMIF offers an additional parameter, TA, that defines the turnaround time between read and write
cycles. This parameter protects against the situation when the output turn-off time of the memory is longer
than the time it takes to start the next write cycle. If this is the case, the EMIF will drive data at the same
time as the memory, causing contention on the bus. By examining Figure 16, the equation for TA can be
derived as:
Figure 16. Timing Waveform of a NAND Flash Read
41
SPRUEQ7C–February 2010 Asynchronous External Memory Interface (EMIF)
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Copyright © 2010, Texas Instruments Incorporated
- User's Guide 1
- SPRUEQ7C–February 2010 2
- Read This First 6
- 1.3 Functional Block Diagram 9
- 2 Architecture 9
- 2.1 Clock Control 9
- 2.2 EMIF Requests 9
- 2.3 Signal Descriptions 10
- 2.4 Pin Multiplexing 10
- Submit Documentation Feedback 11
- Architecture 12
- 3 Use Cases 30
- Use Cases 31
- 3.2 Interfacing to NAND Flash 39
- 4 Registers 48
- Registers 49
- Appendix A Revision History 63
- IMPORTANT NOTICE 64
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