Texas Instruments TMS320DM355 Manual do Utilizador descarregar pdf (Página 123)

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PRODUCT PREVIEW

VCLKIN

(A)

(Positive Edge Clocking)

VCLKIN

(A)

(Negative Edge Clocking)

VCTL

(B)

A. VCLKIN=PCLKorEXTCLK

B. VCTL=HSYNC,VSYNC,andFIELD

VCLKIN

(A)

(Positive Edge Clocking)

VCLKIN

(A)

(Negative Edge Clocking)

VCTL

(B)

A. VCLKIN=PCLKorEXTCLK

B. VCTL=HSYNC,VSYNC,FIELD,andLCD_OE

C. VDATA=COUT[7:0],YOUT[7:0],R[7:3],G[7:2],andB[7:3]

VDATA

(C)

TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007

Figure 5-28. VPBE Input Timing With Respect to PCLK and EXTCLK

Table 5-23. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and

Data Output With Respect to PCLK and EXTCLK

(1) (2) (3)

(see Figure 5-29 )

DM355

NO. PARAMETER UNIT

MIN MAX

11 t

d(VCLKIN-VCTLV)

Delay time, VCLKIN edge to VCTL valid 13.3 ns

12 t

d(VCLKIN-VCTLIV)

Delay time, VCLKIN edge to VCTL invalid 2 ns

13 t

d(VCLKIN-VDATAV)

Delay time, VCLKIN edge to VDATA valid 13.3 ns

14 t

d(VCLKIN-VDATAIV)

Delay time, VCLKIN edge to VDATA invalid 2 ns

(1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the

rising edge of VCLKIN is referenced. When in negative edge clocking mode, the falling edge of VCLKIN is referenced.

(2) VCLKIN = PCLK or EXTCLK

(3) VCTL = HSYNC, VSYNC, FIELD, and LCD_OE

Figure 5-29. VPBE Control and Data Output With Respect to PCLK and EXTCLK

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