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USART Registers: SPI Mode
15-18 USART Peripheral Interface, SPI Mode
UxRXBUF, USART Receive Buffer Register
76543210
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
r r r r r r r r
UxRXBUFx
Bits
7−0
The receive-data buffer is user accessible and contains the last received
character from the receive shift register. Reading UxRXBUF resets the OE
bit and URXIFGx flag. In 7-bit data mode, UxRXBUF is LSB justified and
the MSB is always reset.
UxTXBUF, USART Transmit Buffer Register
76543210
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
rw rw rw rw rw rw rw rw
UxTXBUFx
Bits
7−0
The transmit data buffer is user accessible and contains current data to be
transmitted. When seven-bit character-length is used, the data should be
MSB justified before being moved into UxTXBUF. Data is transmitted MSB
first. Writing to UxTXBUF clears UTXIFGx.
- User’s Guide 1
- Read This First 3
- Glossary 4
- Register Bit Conventions 5
- Contents 10
- Contents 11
- Introduction 14
- 1.1 Architecture 15
- 1.2 Flexible Clock System 15
- 1.3 Embedded Emulation 16
- 1.4 Address Space 17
- 1.4.3 Peripheral Modules 18
- 1.4.5 Memory Organization 18
- System Resets, Interrupts 19
- 2.1.1 Brownout Reset (BOR) 21
- Figure 2−2. Brownout Timing 21
- Software Initialization 22
- 2.2 Interrupts 23
- Reset/NMI Pin 24
- Oscillator Fault 26
- Flash Access Violation 26
- 2.2.2 Maskable Interrupts 27
- 2.2.3 Interrupt Processing 28
- Interrupt Acceptance 28
- Return From Interrupt 29
- 2.2.4 Interrupt Vectors 30
- 2.3 Operating Modes 31
- 2.5 Connection of Unused Pins 34
- 35
- 3.1 CPU Introduction 36
- Figure 3−1. CPU Block Diagram 37
- 3.2 CPU Registers 38
- 3.2.2 Stack Pointer (SP) 39
- Figure 3−3. Stack Pointer 39
- Figure 3−4. Stack Usage 39
- 3.2.3 Status Register (SR) 40
- 3.3 Addressing Modes 43
- 3.3.1 Register Mode 44
- 3.3.2 Indexed Mode 45
- 3.3.3 Symbolic Mode 46
- 3.3.4 Absolute Mode 47
- 3.3.5 Indirect Register Mode 48
- 3.3.7 Immediate Mode 50
- 3.4 Instruction Set 51
- B/W D/S-Reg 53
- 3.4.3 Jumps 54
- Table 3−13.Jump Instructions 54
- Clear carry bit 65
- Clear negative bit 66
- Decrement destination 71
- ] Increment destination 75
- −> PC 78
- No operation 87
- Rotate left arithmetically 92
- Rotate left through carry 93
- Instruction Set 100
- RISC 16−Bit CPU 100
- Instruction Set 101
- 15 8 7 0 102
- → PC −−−− 109
- 110
- 4-3FLL+ Clock Module 112
- 4-4 FLL+ Clock Module 113
- FLL+ Clock Module Operation 114
- 4-5FLL+ Clock Module 114
- 4.2.2 LFXT1 Oscillator 115
- 4.2.3 XT2 Oscillator 115
- DCO Frequency Range 116
- 4.2.6 DCO Modulator 117
- 4.2.9 Buffered Clock Output 118
- Table 4−2.FLL+ Registers 120
- FLL+ Clock Module Registers 122
- 4-13FLL+ Clock Module 122
- 76543210 123
- DCOPLUS XTS_FLL XCAPxPF XT2OF 123
- XT1OF LFOF DCOF 123
- 4-16 FLL+ Clock Module 125
- 126
- 5.1 Flash Memory Introduction 127
- 5.2 Flash Memory Segmentation 128
- 5.3 Flash Memory Operation 129
- 5.3.2 Erasing Flash Memory 130
- Table 5−1.Erase Modes 130
- Initiating an Erase from RAM 132
- 5.3.3 Writing Flash Memory 133
- Table 5−2.Write Modes 133
- Byte/Word Write 133
- Block Write 136
- Block Write Flow and Example 137
- Figure 5−11. Block Write Flow 137
- Flash Memory Operation 140
- 5-15 Flash Memory Controller 140
- - Program via JTAG 140
- 5-16 Flash Memory Controller 141
- 5.4 Flash Memory Registers 142
- Flash Memory Registers 144
- 5-19 Flash Memory Controller 144
- 5-21 Flash Memory Controller 146
- 147
- 6.1 SVS Introduction 148
- Figure 6−1. SVS Block Diagram 149
- 6.2 SVS Operation 150
- 6.2.3 Changing the VLDx Bits 151
- 6.2.4 SVS Operating Range 152
- 6.3 SVS Registers 153
- Hardware Multiplier 154
- 7.2.1 Operand Registers 156
- Table 7−1.OP1 addresses 156
- 7.2.2 Result Registers 157
- Table 7−2.RESHI Contents 157
- Table 7−3.SUMEXT Contents 157
- MACS Underflow and Overflow 157
- 7.2.3 Software Examples 158
- 7.2.5 Using Interrupts 159
- 161
- 8.1 DMA Introduction 162
- 8.2 DMA Operation 164
- 8.2.2 DMA Transfer Modes 165
- Table 8−1.DMA Transfer Modes 165
- Single Transfer 166
- Block Transfers 168
- Burst-Block Transfers 170
- Edge-Sensitive Triggers 172
- Level-Sensitive Triggers 172
- 8.2.4 Stopping DMA Transfers 174
- 8.2.5 DMA Channel Priorities 174
- 8.2.6 DMA Transfer Cycle Time 175
- 8.2.9 Using the I 177
- 8.3 DMA Registers 178
- Digital I/O 184
- 9.1 Digital I/O Introduction 185
- 9.2 Digital I/O Operation 186
- Digital I/O Operation 187
- 9-4 Digital I/O 187
- 9.2.5 P1 and P2 Interrupts 188
- Interrupt Enable P1IE, P2IE 189
- 9.3 Digital I/O Registers 190
- Chapter 10 191
- Watchdog Timer Introduction 193
- 10.2 Watchdog Timer Operation 194
- 10.2.5 WDT+ Enhancements 195
- 10.2.7 Software Examples 196
- 10.3 Watchdog Timer Registers 197
- Watchdog Timer Registers 199
- 201
- Basic Timer1 Introduction 203
- 11-3Basic Timer1 203
- 11.2 Basic Timer1 Operation 204
- 11-5Basic Timer1 205
- 11.3 Basic Timer1 Registers 206
- 11-8 Basic Timer1 208
- 11-9Basic Timer1 209
- Chapter 12 210
- 12.1 Timer_A Introduction 211
- Timer_A Introduction 212
- 12-3Timer_A 212
- 12.2 Timer_A Operation 213
- 12.2.2 Starting the Timer 214
- 12.2.3 Timer Mode Control 214
- Table 12−1.Timer Modes 214
- Figure 12−2. Up Mode 215
- Continuous Mode 216
- Figure 12−4. Continuous Mode 216
- Use of the Continuous Mode 217
- Up/Down Mode 218
- Figure 12−7. Up/Down Mode 218
- Use of the Up/Down Mode 219
- 12.2.4 Capture/Compare Blocks 220
- Capture Mode 220
- Figure 12−11.Capture Cycle 221
- Compare Mode 221
- 12.2.5 Output Unit 222
- Output Modes 222
- Table 12−2.Output Modes 222
- Timer_A Operation 223
- 12-14 Timer_A 223
- 12-15Timer_A 224
- 12-16 Timer_A 225
- 12.2.6 Timer_A Interrupts 226
- TACCR0 Interrupt 226
- 12-18 Timer_A 227
- 12.3 Timer_A Registers 228
- TAR, Timer_A Register 230
- Chapter 13 233
- 13.1 Timer_B Introduction 234
- Timer_B Introduction 235
- 13-3Timer_B 235
- 13.2 Timer_B Operation 236
- 13.2.2 Starting the Timer 237
- 13.2.3 Timer Mode Control 237
- Table 13−1.Timer Modes 237
- Figure 13−2. Up Mode 238
- Figure 13−4. Continuous Mode 239
- Figure 13−7. Up/Down Mode 241
- 13.2.4 Capture/Compare Blocks 243
- Figure 13−11.Capture Cycle 244
- Table 13−2.TBCLx Load Events 245
- 13.2.5 Output Unit 246
- Table 13−4.Output Modes 246
- Timer_B Operation 247
- 13-15Timer_B 247
- 13-16 Timer_B 248
- 13-17Timer_B 249
- 13.2.6 Timer_B Interrupts 250
- 13-19Timer_B 251
- 13.3 Timer_B Registers 252
- TBR, Timer_B Register 254
- Chapter 14 258
- USART Introduction: UART Mode 260
- 14.2.2 Character Format 261
- Figure 14−2. Character Format 261
- Figure 14−3. Idle-Line Format 262
- USART Operation: UART Mode 263
- Automatic Error Detection 265
- 14.2.4 USART Receive Enable 266
- 14.2.5 USART Transmit Enable 267
- Baud Rate Bit Timing 269
- Transmit Bit Timing 270
- Receive Bit Timing 271
- Figure 14−9. Receive Error 271
- Typical Baud Rates and Errors 273
- 14.2.7 USART Interrupts 274
- UxCTL, USART Control Register 279
- USART Registers: UART Mode 282
- UxRXBUFx 283
- UxTXBUFx 283
- ME1, Module Enable Register 1 284
- ME2, Module Enable Register 2 284
- Chapter 15 287
- USART Introduction: SPI Mode 289
- 15.2.2 Master Mode 291
- Four-Pin SPI Master Mode 291
- 15.2.3 Slave Mode 292
- Four-Pin SPI Slave Mode 292
- 15.2.4 SPI Enable 293
- Transmit Enable 293
- Receive Enable 294
- 15.2.5 Serial Clock Control 295
- Figure 15−9. USART SPI Timing 296
- 15.2.6 SPI Interrupts 297
- USART Operation: SPI Mode 298
- USART Registers: SPI Mode 303
- Chapter 16 308
- 16.1 OA Introduction 309
- Figure 16−1. OA Block Diagram 310
- 16.2 OA Operation 311
- 16.2.4 OA Configurations 312
- Table 16−1.OA Mode Select 312
- General Purpose Opamp Mode 312
- Unity Gain Mode 312
- Comparator Mode 312
- Non-Inverting PGA Mode 313
- Inverting PGA Mode 313
- Differential Amplifier Mode 313
- 16-10 OA 317
- 16.3 OA Registers 318
- OANx OAPx OAPMx OAADC1 OAADC0 319
- OAFBRx OAFCx Reserved OARRIP 320
- Comparator_A 321
- Comparator_A Introduction 323
- 17-3Comparator_A 323
- 17.2 Comparator_A Operation 324
- 17.2.3 Output Filter 325
- 17.3 Comparator_A Registers 329
- LCD Controller 332
- LCD Controller Introduction 334
- 18-3LCD Controller 334
- 18.2 LCD Controller Operation 335
- 18.2.4 LCD Voltage Generation 336
- LCD Contrast Control 336
- 18.2.5 LCD Outputs 336
- 18.2.6 Static Mode 337
- Static Mode Software Example 339
- 18.2.7 2-Mux Mode 340
- 2-Mux Mode Software Example 342
- 18.2.8 3-Mux Mode 343
- 3-Mux Mode Software Example 345
- 18.2.9 4-Mux Mode 346
- 4-Mux Mode Software Example 348
- 18.3 LCD Controller Registers 349
- LCDCTL, LCD Control Register 350
- LCD_A Controller 351
- LCD_A Controller Introduction 353
- 19-3LCD_A Controller 353
- 19.2.1 LCD Memory 354
- Figure 19−2. LCD memory 354
- 19.2.2 Blinking the LCD 354
- LCD Voltage Selection 355
- LCD Bias Generation 355
- Figure 19−3. Bias Generation 356
- 19.2.4 LCD Timing Generation 358
- 19.2.5 LCD Outputs 358
- 19.2.6 Static Mode 359
- 19.2.7 2-Mux Mode 362
- 19.2.8 3-Mux Mode 365
- 19.2.9 4-Mux Mode 368
- 19.3 LCD Controller Registers 371
- LCD_A Controller Operation 374
- 19-24 LCD_A Controller 374
- 19-26 LCD_A Controller 376
- Chapter 20 377
- 20.1 ADC12 Introduction 378
- †MSP430FG43x devices only 379
- 20.2 ADC12 Operation 380
- Analog Port Selection 381
- 20.2.4 Auto Power-Down 382
- Extended Sample Mode 383
- Pulse Sample Mode 384
- Sample Timing Considerations 385
- 20.2.6 Conversion Memory 386
- 20.2.7 ADC12 Conversion Modes 386
- x = pointer to ADC12MCTLx 387
- Sequence-of-Channels Mode 388
- Repeat-Single-Channel Mode 389
- Stopping Conversions 391
- ADC12 Operation 392
- 20-16 ADC12 392
- 20-17ADC12 393
- 20.2.10 ADC12 Interrupts 394
- 20.3 ADC12 Registers 396
- ADC12 Registers 401
- 20-25ADC12 401
- 20-26 ADC12 402
- ADC12IEx 402
- ADC12IFGx 402
- ADC12 interrupt vector value 403
- Chapter 21 404
- 21.1 SD16 Introduction 405
- SD16 Introduction 406
- 21-3SD16 406
- 21.2 SD16 Operation 407
- Analog Input Setup 408
- 21.2.6 Digital Filter 409
- SD16 Operation 410
- 21-7SD16 410
- Digital Filter Output 411
- ZERO 8000 800000 412
- 21.2.8 Conversion Modes 413
- 21-11SD16 414
- 21-12 SD16 415
- 21-13SD16 416
- 21-14 SD16 417
- 21-15SD16 418
- 21.2.11 Interrupt Handling 419
- Interrupt Delay Operation 419
- 21.3 SD16 Registers 421
- 12’s complement 423
- SD16 interrupt vector value 426
- Chapter 22 427
- 22.1 SD16_A Introduction 428
- SD16_A Introduction 429
- 22-3SD16_A 429
- 22.2 SD16_A Operation 430
- 22.2.7 Digital Filter 432
- SD16_A Operation 433
- 22-7SD16_A 433
- 22-9SD16_A 435
- 22.2.9 Conversion Modes 437
- Single Conversion 437
- Continuous Conversion 437
- 22-12 SD16_A 438
- 22.2.11 Interrupt Handling 439
- 22.3 SD16_A Registers 440
- SD16_A Registers 445
- 22-19SD16_A 445
- Conversion 445
- SD16_A interrupt vector value 446
- Chapter 23 447
- 23.1 DAC12 Introduction 448
- DAC12 Introduction 449
- 23-3DAC12 449
- 23-4 DAC12 450
- 23.2 DAC12 Operation 451
- 23.2.2 DAC12 Reference 452
- 23.2.4 DAC12_xDAT Data Format 453
- Figure 23−5. Negative Offset 454
- Figure 23−6. Positive Offset 454
- DAC12 Operation 455
- 23-9DAC12 455
- 23.2.7 DAC12 Interrupts 456
- 23.3 DAC12 Registers 457
- 461
- 24.1 Scan IF Introduction 462
- Scan IF Introduction 463
- 24-3Scan IF 463
- 24.2 Scan IF Operation 464
- Scan IF Operation 465
- 24-5Scan IF 465
- Excitation 466
- Mid-Voltage Generator 466
- 24-7Scan IF 467
- Sample-And-Hold 468
- 24-10 Scan IF 470
- Comparator and DAC 471
- 24-13Scan IF 473
- 24-14 Scan IF 474
- 24-15Scan IF 475
- TSM Operation 476
- TSM Control of the AFE 476
- TSM State Duration 476
- Table 24−5.TSM State Duration 476
- TSM State Clock Source Select 477
- TSM Stop Condition 477
- TSM Test Cycles 478
- TSM Example 479
- 24-20 Scan IF 480
- PSM Operation 481
- Next State Calculation 482
- PSM Counters 483
- Simplest State Machine 484
- 24.2.4 Scan IF Debug Register 486
- 24.2.5 Scan IF Interrupts 487
- Table 24−7.Scan IF Interrupts 487
- 24-28 Scan IF 488
- 24-29Scan IF 489
- 24-30 Scan IF 490
- 24-31Scan IF 491
- 24-32 Scan IF 492
- 24.2.8 Quadrature Decoding 493
- 24.3 Scan IF Registers 495
- Scan IF Registers 496
- 24-36 Scan IF 496
- Reserved 496
- SIFDEBUGx 496
- Last PSM 496
- 24-37Scan IF 497
- TSM Index 497
- PSM Bits 497
- 24-39Scan IF 499
- SIFCNT2x 499
- SIFCNT1x 499
- SIFPSMVx 499
- 24-41Scan IF 501
- SIFTESTD 501
- 24-49Scan IF 509
- DAC Data 509
- Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 512
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