Texas-instruments TMS320C6452 DSP Manual do Utilizador

TMS320C6452 DSPDDR2 Memory ControllerUser's GuideLiterature Number: SPRUF85October 2007

www.ti.comL1 S1 M1 D1Data path ARegister file A Register file BD2Data path BS2M2 L2L1 data memory controllerCache controlMemory protectionInterruptand

www.ti.com2 Peripheral Architecture2.1 Clock Control2.2 Memory Map2.3 Signal DescriptionsPeripheral ArchitectureThe DDR2 memory controller can glueles

www.ti.comDDR_D[31:0]DDR2memorycontrollerDDR_CLKDDR_CLKDDR_CSDDR_CKEDDR_RASDDR_WEDDR_DQM[3:0]DDR_CASDDR_BA[2:0]DDR_DQS[3:0]DDR_A[13:0]DDR_VREFDDR_DQGA

www.ti.com2.4 Protocol Description(s)Peripheral ArchitectureThe DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 2 . Table 3 sh

www.ti.com2.4.1 Mode Register Set (MRS and EMRS)COLMRS/EMRSBANKDDR_CLKDDR_CLKDDR_CSDDR_CKEDDR_RASDDR_WEDDR_CASDDR_BA[2:0]DDR_A[13:0]2.4.2 Refresh Mode

www.ti.comREFRDDR_CLKDDR_CLKDDR_CSDDR_CKEDDR_RASDDR_WEDDR_DQM[3:0]DDR_CASDDR_BA[2:0]DDR_A[13:0]2.4.3 Activation (ACTV)ACTVBANKROWDDR_CLKDDR_CLKDDR_CSD

www.ti.com2.4.4 Deactivation (DCAB and DEAC)DCABDDR_CLKDDR_CLKDDR_CSDDR_CKEDDR_RASDDR_WEDDR_DQM[3:0]DDR_CASDDR_BA[2:0]DDR_A[13:11, 9:0]DDR_A[10]DEACDD

www.ti.com2.4.5 READ CommandDDR_D[31:0]DDR_DQS[3:0]COLBANKDDR_A[10]CAS LatencyD0 D1 D2 D3 D4 D5 D6 D7DDR_CLKDDR_CLKDDR_CSDDR_CKEDDR_RASDDR_WEDDR_DQM[3

www.ti.com2.4.6 Write (WRT) CommandDDR_D[31:0]DDR_DQS[3:0]COLBANKDQM7SampleD0 D1 D2 D3 D4 D5 D6 D7DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM8Write LatencyDDR_A

www.ti.comDDR2 memory controller data busDDR_D[31:24](Byte Lane 3)DDR_D[23:16](Byte Lane 2)DDR_D[15:8](Byte Lane 1)DDR_D[7:0](Byte Lane 0)32-bit memor

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www.ti.comPeripheral ArchitectureSDCFG Bit Logical AddressIBANK PAGESIZE 31:28 27 26 25 24 23 22:17 16 15 14 13 12 11 10 9:20 0 X X X X X nrb=14(1)ncb

www.ti.comCol. 0 Col. 1 Col. 2 Col. 3 Col. 4 Col. M−1 Col. MRow 0, bank 0Row 0, bank 1Row 0, bank 2Row 0, bank PRow 1, bank 1Row 1, bank 0Row 1, bank

www.ti.com0 1 2 3 MBank 0Row 0Row 1Row 2Row NCol lColColCoRow 0Row NRow 1Row 2CCBank 1l l0 21ooC Cl l3 Mo oRow 0Row NRow 1Row 2CCBank 2l l0 21oollllRo

www.ti.comCommand/DataSchedulerCommand FIFOWrite FIFORead FIFORegistersCommandto MemoryWrite Datato MemoryRead DatafromMemoryCommandDataEDMA BUS2.7.1

www.ti.com2.7.2 Command StarvationPeripheral ArchitectureNext, the DDR2 memory controller examines each of the commands selected by the individual mas

www.ti.com2.7.3 Possible Race Condition2.8 Refresh SchedulingPeripheral ArchitectureA race condition may exist when certain masters write data to the

www.ti.com2.9 Self-Refresh Mode2.10 Reset ConsiderationsHardresetfromPLLCTL1DDRPSCDDR2memorycontrollerregistersStatemachineVRSTVCTL_RSTPeripheral Arc

www.ti.com2.11 DDR2 SDRAM Memory Initialization2.11.1 DDR2 SDRAM Device Mode Register Configuration ValuesPeripheral ArchitectureDDR2 SDRAM devices co

www.ti.com2.11.2 DDR2 SDRAM Initialization After Reset2.11.3 DDR2 SDRAM Initialization After Register Configuration2.12 Interrupt Support2.13 EDMA Eve

www.ti.com3 Using the DDR2 Memory Controller3.1 Connecting the DDR2 Memory Controller to DDR2 SDRAMUsing the DDR2 Memory ControllerThe following secti

ContentsPreface ... 61 Int

www.ti.comCKCKCKECSWERASCASLDMUDMLDQSUDQSBA[2:0]A[12:0]DQ[15:0]VREFDDR2memoryx16−bitLDQSUDQSDDR_CLKDDR_CLKDDR_CKEDDR_CSDDR_WEDDR_RASDDR_DQM0DDR_CASDDR

www.ti.comDDR_CLKDDR_CLKDDR_CKEDDR_CSDDR_WEDDR_RASDDR_CASDDR_DQM0DDR_DQM1DDR_DQS0DDR_DQS1DDR_BA[2:0]DDR_A[13:0]DDR_D[15:0]DDR_VREFDDR_ODT0DDR_DQS0DDR_

www.ti.comCKCKCKECSWERASCASDMDQSBA[2:0]A[13:0]DQ[7:0]VREFDDR2memoryx8−bitDQSRDQSDDR_CLKDDR_CLKDDR_CKEDDR_CSDDR_WEDDR_RASDDR_DQM0DDR_CASDDR_DQS0DDR_DQS

www.ti.com3.2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications3.2.1 Programming the SDRAM Configuration Register (SDCFG)

www.ti.com3.2.3 Configuring SDRAM Timing Registers (SDTIM1 and SDTIM2)Using the DDR2 Memory ControllerTable 12 displays the DDR2-533 refresh rate spec

www.ti.com3.2.4 Configuring the DDR2 Memory Controller Control Register (DMCCTL)Using the DDR2 Memory ControllerTable 15. SDTIM2 ConfigurationDDR2 SDR

www.ti.com4 DDR2 Memory Controller RegistersDDR2 Memory Controller RegistersTable 17 lists the memory-mapped registers for the DDR2 memory controller.

www.ti.com4.1 Module ID and Revision Register (MIDR)4.2 DDR2 Memory Controller Status Register (DMCSTAT)DDR2 Memory Controller RegistersThe Module ID

www.ti.com4.3 SDRAM Configuration Register (SDCFG)DDR2 Memory Controller RegistersThe SDRAM configuration register (SDCFG) contains fields that progra

www.ti.comDDR2 Memory Controller RegistersTable 20. SDRAM Configuration Register (SDCFG) Field Descriptions (continued)Bit Field Value Description11-9

List of Figures1 DDR2 Memory Controller Block Diagram ... 102 DDR2 Memory

www.ti.com4.4 SDRAM Refresh Control Register (SDRFC)DDR2 Memory Controller RegistersThe SDRAM refresh control register (SDRFC) is used to configure th

www.ti.com4.5 SDRAM Timing 1 Register (SDTIM1)DDR2 Memory Controller RegistersThe SDRAM timing 1 register (SDTIM1) configures the DDR2 memory controll

www.ti.comDDR2 Memory Controller RegistersTable 22. SDRAM Timing 1 Register (SDTIM1) Field Descriptions (continued)Bit Field Value Description1-0 T_WT

www.ti.com4.6 SDRAM Timing 2 Register (SDTIM2)DDR2 Memory Controller RegistersLike the SDRAM timing 1 register (SDTIM1), the SDRAM timing 2 register (

www.ti.com4.7 Burst Priority Register (BPRIO)DDR2 Memory Controller RegistersThe Burst Priority Register (BPRIO) helps prevent command starvation with

www.ti.com4.8 DDR2 Memory Controller Control Register (DMCCTL)DDR2 Memory Controller RegistersThe DDR2 memory controller control register (DMCCTL) res

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,improvemen

List of Tables1 DDR2 Memory Controller Signal Descriptions ... 122 DDR2 SDRAM Co

PrefaceSPRUF85 – October 2007Read This FirstAbout This ManualThis document describes the operation of the DDR2 Memory Controller in the TMS320C6452.No

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1 Introduction1.1 Purpose of the Peripheral1.2 Features1.3 Functional Block DiagramUser's GuideSPRUF85 – October 2007DSP DDR2 Memory ControllerTh