manuais Texas Instruments MSP430x1xx

Texas instruments MSP430x1xx Manual do Utilizador (432 páginas)

Marca: Texas-instruments | Categoria: Geradores de energia | Tamanho: 1.54 MB |

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Índice

User’s Guide

1



3

Glossary

4

Register Bit Conventions

5



7

Contents

9

Contents

10



13

1.1 Architecture

14

1.2 Flexible Clock System

14

1.3 Embedded Emulation

15

1.4 Address Space

16

1.4.3 Peripheral Modules

17

1.4.5 Memory Organization

17

Introduction

18



19



19

2.1.1 Power-On Reset (POR)

21

Figure 2−2. POR Timing

21

2.1.2 Brownout Reset (BOR)

22

Figure 2−3. Brownout Timing

22

Software Initialization

23

2.2 Interrupts

24

Reset/NMI Pin

25

Flash Access Violation

27

Oscillator Fault

27

2.2.2 Maskable Interrupts

28

2.2.3 Interrupt Processing

29

Interrupt Acceptance

29

Return From Interrupt

30

Interrupt Nesting

30

2.2.4 Interrupt Vectors

31

2.3 Operating Modes

32

2.5 Connection of Unused Pins

35

  !

37

3.1 CPU Introduction

38

Figure 3−1. CPU Block Diagram

39

3.2 CPU Registers

40

3.2.2 Stack Pointer (SP)

41

Figure 3−3. Stack Pointer

41

Figure 3−4. Stack Usage

41

3.2.3 Status Register (SR)

42

3.3 Addressing Modes

45

3.3.1 Register Mode

46

3.3.2 Indexed Mode

47

3.3.3 Symbolic Mode

48

3.3.4 Absolute Mode

49

3.3.5 Indirect Register Mode

50

3.3.7 Immediate Mode

52

3.4 Instruction Set

53

B/W D/S-Reg

55

3.4.3 Jumps

56

Table 3−13.Jump Instructions

56

Clear carry bit

67

Clear negative bit

68

Decrement destination

73

] Increment destination

77

Jump if greater or equal

82

Jump if less

83

Jump unconditionally

84

Jump if negative

85

No operation

89

Rotate left arithmetically

94

Rotate left through carry

95

Instruction Set

100

RISC 16−Bit CPU

100

Instruction Set

101

15 8 7 0

104

→ PC − − − −

111

Chapter 4

113

Note: XT2 Oscillator

115

Basic Clock Module Operation

116

Basic Clock Module

116

4.2.2 LFXT1 Oscillator

117

4.2.3 XT2 Oscillator

118

Disabling the DCO

118

Adjusting the DCO frequency

119

Using an External Resistor (R

120

) for the DCO

120

4.2.5 DCO Modulator

121

Oscillator Fault Detection

123

Sourcing MCLK from a Crystal

124

DCOCTL, DCO Control Register

127

76543210

128

SELMx DIVMx SELS DIVSx DCOR

128

Basic Clock Module Registers

129

Chapter 5

131

5.1 Flash Memory Introduction

132

5.2 Flash Memory Segmentation

133

5.3 Flash Memory Operation

134

5.3.2 Erasing Flash Memory

135

Table 5−1.Erase Modes

135

Initiating an Erase from RAM

137

5.3.3 Writing Flash Memory

138

Table 5−2.Write Modes

138

Byte/Word Write

138

Block Write

141

Block Write Flow and Example

142

Figure 5−11. Block Write Flow

142

Flash Memory Operation

146

Flash Memory Controller

146

5.4 Flash Memory Registers

147

Flash Memory Registers

151

Chapter 6

153

6.1 SVS Introduction

154

Figure 6−1. SVS Block Diagram

155

6.2 SVS Operation

156

6.2.3 Changing the VLDx Bits

157

6.2.4 SVS Operating Range

158

6.3 SVS Registers

159

Supply Voltage Supervisor

160

Chapter 7

161

7.2.1 Operand Registers

163

Table 7−1.OP1 addresses

163

7.2.2 Result Registers

164

Table 7−2.RESHI Contents

164

Table 7−3.SUMEXT Contents

164

MACS Underflow and Overflow

164

7.2.3 Software Examples

165

7.2.5 Using Interrupts

166

Hardware Multiplier

168

() ""

169

8.1 DMA Introduction

170

8.2 DMA Operation

172

8.2.2 DMA Transfer Modes

173

Table 8−1.DMA Transfer Modes

173

Single Transfer

174

Block Transfers

176

Burst-Block Transfers

178

Edge-Sensitive Triggers

180

Level-Sensitive Triggers

180

8.2.4 Stopping DMA Transfers

182

8.2.5 DMA Channel Priorities

182

8.2.6 DMA Transfer Cycle Time

183

8.2.9 Using the I

185

8.3 DMA Registers

186

("*

193

9.1 Digital I/O Introduction

194

9.2 Digital I/O Operation

195

Digital I/O Operation

196

Digital I/O

196

9.2.5 P1 and P2 Interrupts

197

Interrupt Enable P1IE, P2IE

198

9.3 Digital I/O Registers

199

+ 

201

Watchdog Timer Introduction

203

Watchdog Timer

203

10.2 Watchdog Timer Operation

204

Watchdog Timer Operation

205

10.2.6 Software Examples

206

10.3 Watchdog Timer Registers

207

Watchdog Timer Registers

209

Chapter 11

211

11.1 Timer_A Introduction

212

Timer_A Introduction

213

11.2 Timer_A Operation

214

11.2.2 Starting the Timer

215

11.2.3 Timer Mode Control

215

Table 11−1.Timer Modes

215

Figure 11−2. Up Mode

216

Continuous Mode

217

Figure 11−4. Continuous Mode

217

Use of the Continuous Mode

218

Up/Down Mode

219

Figure 11−7. Up/Down Mode

219

Use of the Up/Down Mode

220

11.2.4 Capture/Compare Blocks

221

Capture Mode

221

Figure 11−11.Capture Cycle

222

Compare Mode

222

11.2.5 Output Unit

223

Output Modes

223

Table 11−2.Output Modes

223

Timer_A Operation

224

11.2.6 Timer_A Interrupts

227

TACCR0 Interrupt

227

11.3 Timer_A Registers

229

TAR, Timer_A Register

231

Chapter 12

235

12.1 Timer_B Introduction

236

Timer_B Introduction

237

12.2 Timer_B Operation

238

12.2.2 Starting the Timer

239

12.2.3 Timer Mode Control

239

Table 12−1.Timer Modes

239

Figure 12−2. Up Mode

240

Figure 12−4. Continuous Mode

241

Figure 12−7. Up/Down Mode

243

12.2.4 Capture/Compare Blocks

245

Figure 12−11.Capture Cycle

246

Table 12−2.TBCLx Load Events

247

12.2.5 Output Unit

248

Table 12−4.Output Modes

248

Timer_B Operation

249

12.2.6 Timer_B Interrupts

252

12.3 Timer_B Registers

254

TBR, Timer_B Register

256

Chapter 13

261

USART Introduction: UART Mode

263

13.2.2 Character Format

264

Figure 13−2. Character Format

264

Figure 13−3. Idle-Line Format

265

USART Operation: UART Mode

266

Automatic Error Detection

268

13.2.4 USART Receive Enable

269

13.2.5 USART Transmit Enable

270

Baud Rate Bit Timing

272

Transmit Bit Timing

273

Receive Bit Timing

274

Figure 13−9. Receive Error

274

Typical Baud Rates and Errors

276

13.2.7 USART Interrupts

277

UxCTL, USART Control Register

282

USART Registers: UART Mode

285

UxRXBUFx

286

UxTXBUFx

286

ME1, Module Enable Register 1

287

ME2, Module Enable Register 2

287

Chapter 14

292

USART Introduction: SPI Mode

294

14.2.2 Master Mode

296

Four-Pin SPI Master Mode

296

14.2.3 Slave Mode

297

Four-Pin SPI Slave Mode

297

14.2.4 SPI Enable

298

Transmit Enable

298

Receive Enable

299

14.2.5 Serial Clock Control

300

Figure 14−9. USART SPI Timing

301

14.2.6 SPI Interrupts

302

USART Operation: SPI Mode

303

USART Registers: SPI Mode

308

Chapter 15

315

C Module Introduction

316

USART Peripheral Interface, I

317

C Module Operation

318

15.2.1 I

319

C Module Initialization

319

15.2.4 I

322

C Module Operating Modes

322

Master Mode

322

Table 15−1.Master Operation

322

Slave Mode

326

Figure 15−12. Slave Receiver

328

15.2.5 The I

329

C Data Register I2CDR

329

Transmit Underflow

329

Receive Overrun

329

15.2.7 Using the I

331

C Module with Low Power Modes

331

15.2.8 I

332

C Interrupts

332

Table 15−3.I

332

RETI ; Vector 0: No interrupt

333

C Module Registers

334

I2CTCTL, I

336

C Transmit Control Register

336

I2CDCTL, I

337

C Data Control Register

337

I2CDRW, I2CDRB, I

338

C Data Register

338

I2CNDAT, I

338

I2CPSC, I

339

C Clock Prescaler Register

339

I2CSCLH, I

340

C Shift Clock High Register

340

I2CSCLL, I

340

C Shift Clock Low Register

340

I2COA, I

341

I2CSA, I

342

I2CIE, I

343

C Interrupt Enable Register

343

I2CIFG, I

344

C Interrupt Flag Register

344

I2CIV, I

345

C Interrupt Vector Register

345

,)

347

Comparator_A Introduction

349

Comparator_A

349

16.2 Comparator_A Operation

350

16.2.3 Output Filter

351

16.3 Comparator_A Registers

355

Chapter 17

359

17.1 ADC12 Introduction

360

ADC12 Introduction

361

17.2 ADC12 Operation

362

Analog Port Selection

363

17.2.4 Auto Power-Down

364

Extended Sample Mode

365

Pulse Sample Mode

366

Sample Timing Considerations

367

17.2.6 Conversion Memory

368

17.2.7 ADC12 Conversion Modes

368

x = pointer to ADC12MCTLx

369

Sequence-of-Channels Mode

370

Repeat-Single-Channel Mode

371

Stopping Conversions

373

ADC12 Operation

374

17.2.10 ADC12 Interrupts

376

17.3 ADC12 Registers

378

EOS SREFx INCHx

383

Modifiable only when ENC = 0

383

ADC12 Registers

384

ADC12IEx

384

ADC12IFGx

384

ADC12 interrupt vector value

385

Chapter 18

387

18.1 ADC10 Introduction

388

ADC10 Introduction

389

18.2 ADC10 Operation

390

18.2.4 Auto Power-Down

392

Figure 18−3. Sample Timing

393

18.2.6 Conversion Modes

395

Using the MSC Bit

400

ADC10 Operation

401

One-Block Transfer Mode

402

Two-Block Transfer Mode

404

Continuous Transfer

406

DTC Transfer Cycle Time

406

18.2.10 ADC10 Interrupts

409

18.3 ADC10 Registers

410

Chapter 19

419

19.1 DAC12 Introduction

420

DAC12 Introduction

421

19.2 DAC12 Operation

422

19.2.2 DAC12 Reference

423

19.2.4 DAC12_xDAT Data Format

424

Figure 19−4. Negative Offset

425

Figure 19−5. Positive Offset

425

19.2.7 DAC12 Interrupts

427

19.3 DAC12 Registers

428

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