Texas Instruments MSP430x1xx Manual do Utilizador

  2005 Mixed Signal ProductsUser’s GuideSLAU049E

Contentsx10 Watchdog Timer 10-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Instruction Set3-64 RISC 16−Bit CPU* SETN Set negative bitSyntax SETNOperation 1 −> NEmulation BIS #4,SRDescription The negative bit (N) is set.St

Instruction Set3-65 RISC 16−Bit CPU* SETZ Set zero bitSyntax SETZOperation 1 −> ZEmulation BIS #2,SRDescription The zero bit (Z) is set.Status Bit

Instruction Set3-66 RISC 16−Bit CPUSUB[.W] Subtract source from destinationSUB.B Subtract source from destinationSyntax SUB src,dst or SUB.W src,dstS

Instruction Set3-67 RISC 16−Bit CPUSUBC[.W]SBB[.W] Subtract source and borrow/.NOT. carry from destinationSUBC.B,SBB.B Subtract source and borrow/

Instruction Set3-68 RISC 16−Bit CPUSWPB Swap bytesSyntax SWPB dstOperation Bits 15 to 8 <−> bits 7 to 0Description The destination operand high

Instruction Set3-69 RISC 16−Bit CPUSXT Extend SignSyntax SXT dstOperation Bit 7 −> Bit 8 ... Bit 15Description The sign of the low byte is e

Instruction Set3-70 RISC 16−Bit CPU* TST[.W] Test destination* TST.B Test destinationSyntax TST dst or TST.W dstTST.B dstOperation dst + 0FFFFh + 1dst

Instruction Set3-71 RISC 16−Bit CPUXOR[.W] Exclusive OR of source with destinationXOR.B Exclusive OR of source with destinationSyntax XOR src,dst or

Instruction Set3-72 RISC 16−Bit CPU3.4.4 Instruction Cycles and LengthsThe number of CPU clock cycles required for an instruction depends on theinstru

Instruction Set3-73 RISC 16−Bit CPUFormat-I (Double Operand) Instruction Cycles and LengthsTable 3−16 lists the length and CPU cycles for all address

Contentsxi 14 USART Peripheral Interface, SPI Mode 14-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1 USA

Instruction Set3-74 RISC 16−Bit CPU3.4.5 Instruction Set DescriptionThe instruction map is shown in Figure 3−20 and the complete instruction setis sum

Instruction Set3-75 RISC 16−Bit CPUTable 3−17.MSP430 Instruction SetMnemonic Description V N Z CADC(.B)†dst Add C to destination dst + C → dst * * *

3-76

4-1Basic Clock Module  "# "The basic clock module provides the clocks for MSP430x1xx devices. Thischapter describes the opera

Basic Clock Module Introduction4-2Basic Clock Module4.1 Basic Clock Module IntroductionThe basic clock module supports low system cost and ultralow-po

Basic Clock Module Introduction4-3Basic Clock ModuleFigure 4−1. Basic Clock Block DiagramDivider/1/2/4/8DIVAxMCLKCPUOFFDCOCLKXINXOUTDCORP2.5/RoscLFXT1

Basic Clock Module Operation4-4Basic Clock Module4.2 Basic Clock Module OperationAfter a PUC, MCLK and SMCLK are sourced from DCOCLK at ~800 kHz (seed

Basic Clock Module Operation4-5Basic Clock Module4.2.2 LFXT1 OscillatorThe LFXT1 oscillator supports ultralow-current consumption using a32,768-Hz wat

Basic Clock Module Operation4-6Basic Clock Module4.2.3 XT2 OscillatorSome devices have a second crystal oscillator, XT2. XT2 sources XT2CLKand its cha

Basic Clock Module Operation4-7Basic Clock ModuleAdjusting the DCO frequencyAfter a PUC, the internal resistor is selected for the DC generator, RSELx

Contentsxii18 ADC10 18-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Basic Clock Module Operation4-8Basic Clock ModuleUsing an External Resistor (ROSC) for the DCOThe DCO temperature coefficient can be reduced by using

Basic Clock Module Operation4-9Basic Clock Module4.2.5 DCO ModulatorThe modulator mixes two DCO frequencies, fDCO and fDCO+1 to produce anintermediate

Basic Clock Module Operation4-10Basic Clock Module4.2.6 Basic Clock Module Fail-Safe OperationThe basic clock module incorporates an oscillator-fault

Basic Clock Module Operation4-11Basic Clock ModuleOscillator Fault DetectionSignal XT_OscFault triggers the OFIFG flag as shown in Figure 4−10. TheLFX

Basic Clock Module Operation4-12Basic Clock ModuleSourcing MCLK from a CrystalAfter a PUC, the basic clock module uses DCOCLK for MCLK. If required,MC

Basic Clock Module Operation4-13Basic Clock Module4.2.7 Synchronization of Clock SignalsWhen switching MCLK or SMCLK from one clock source to the anot

Basic Clock Module Registers 4-14Basic Clock Module4.3 Basic Clock Module Registers The basic clock module registers are listed in Table 4−1:Table 4−1

Basic Clock Module Registers 4-15Basic Clock ModuleDCOCTL, DCO Control Register76543210DCOx MODxrw−0 rw−1 rw−1 rw−0 rw−0 rw−0 rw−0 rw−0DCOxBits7-5DCO

Basic Clock Module Registers 4-16Basic Clock ModuleBCSCTL2, Basic Clock System Control Register 276543210SELMx DIVMx SELS DIVSx DCORrw−(0) rw−(0) rw−(

Basic Clock Module Registers 4-17Basic Clock ModuleIE1, Interrupt Enable Register 176543210OFIErw−0Bits7-2These bits may be used by other modules. See

1-1Introduction This chapter describes the architecture of the MSP430.Topic Page1.1 Architecture 1-2. . . . . . . . . . . . . . . . . . .

4-18Basic Clock Module

5-1 Flash Memory Controller "  ""This chapter describes the operation of the MSP430 flash memory controller.Topic

Flash Memory Introduction5-2 Flash Memory Controller5.1 Flash Memory IntroductionThe MSP430 flash memory is bit-, byte-, and word-addressable andprogr

Flash Memory Segmentation5-3 Flash Memory Controller5.2 Flash Memory SegmentationMSP430 flash memory is partitioned into segments. Single bits, bytes,

Flash Memory Operation5-4 Flash Memory Controller5.3 Flash Memory OperationThe default mode of the flash memory is read mode. In read mode, the flashm

Flash Memory Operation5-5 Flash Memory Controller5.3.2 Erasing Flash MemoryThe erased level of a flash memory bit is 1. Each bit can be programmed fro

Flash Memory Operation5-6 Flash Memory ControllerInitiating an Erase from Within Flash MemoryAny erase cycle can be initiated from within flash memory

Flash Memory Operation5-7 Flash Memory ControllerInitiating an Erase from RAMAny erase cycle may be initiated from RAM. In this case, the CPU is not h

Flash Memory Operation5-8 Flash Memory Controller5.3.3 Writing Flash MemoryThe write modes, selected by the WRT and BLKWRT bits, are listed inTable 5−

Flash Memory Operation5-9 Flash Memory ControllerIn byte/word mode, the internally-generated programming voltage is appliedto the complete 64-byte blo

Architecture1-2Introduction1.1 ArchitectureThe MSP430 incorporates a 16-bit RISC CPU, peripherals, and a flexible clocksystem that interconnect using

Flash Memory Operation5-10 Flash Memory ControllerInitiating a Byte/Word Write from RAMThe flow to initiate a byte/word write from RAM is shown in Fig

Flash Memory Operation5-11 Flash Memory ControllerBlock WriteThe block write can be used to accelerate the flash write process when manysequential byt

Flash Memory Operation5-12 Flash Memory ControllerBlock Write Flow and ExampleA block write flow is shown in Figure 5−8 and the following example.Figu

Flash Memory Operation5-13 Flash Memory Controller; Write one block starting at 0F000h.; Must be executed from RAM, Assumes Flash is already erased.;

Flash Memory Operation5-14 Flash Memory Controller5.3.4 Flash Memory Access During Write or EraseWhen any write or any erase operation is initiated fr

Flash Memory Operation5-15 Flash Memory Controller5.3.5 Stopping a Write or Erase CycleAny write or erase operation can be stopped before its normal c

Flash Memory Operation5-16 Flash Memory ControllerProgramming Flash Memory via JTAGMSP430 devices can be programmed via the JTAG port. The JTAG interf

Flash Memory Registers5-17 Flash Memory Controller5.4 Flash Memory RegistersThe flash memory registers are listed in Table 5−4.Table 5−4.Flash Memory

Flash Memory Registers5-18 Flash Memory ControllerFCTL1, Flash Memory Control Register15 14 13 12 11 10 9 8FRKEY, Read as 096hFWKEY, Must be written a

Flash Memory Registers5-19 Flash Memory ControllerFCTL2, Flash Memory Control Register15 14 13 12 11 10 9 8FWKEYx, Read as 096hMust be written as 0A5h

Embedded Emulation1-3IntroductionFigure 1−1. MSP430 ArchitectureACLKBusConv.PeripheralMAB 16-BitMDB 16-BitMCLKSMCLKClockSystemPeripheral PeripheralPer

Flash Memory Registers5-20 Flash Memory ControllerFCTL3, Flash Memory Control Register FCTL315 14 13 12 11 10 9 8FWKEYx, Read as 096hMust be written a

Flash Memory Registers5-21 Flash Memory ControllerIE1, Interrupt Enable Register 176543210ACCVIErw−0Bits7-6,4-0These bits may be used by other modules

5-22 Flash Memory Controller

6-1Supply Voltage Supervisor " $" %This chapter describes the operation of the SVS. The SVS is implemented inMSP430x15x

SVS Introduction6-2Supply Voltage Supervisor6.1 SVS IntroductionThe supply voltage supervisor (SVS) is used to monitor the AVCC supplyvoltage or an ex

SVS Introduction6-3Supply Voltage SupervisorFigure 6−1. SVS Block Diagram+− 1.25VBrownoutResetVCCSet SVSFGtReset ~ 50usResetSVSCTL Bits000100100011111

SVS Operation6-4Supply Voltage Supervisor6.2 SVS OperationThe SVS detects if the AVCC voltage drops below a selectable level. It can beconfigured to p

SVS Operation6-5Supply Voltage Supervisor6.2.3 Changing the VLDx BitsWhen the VLDx bits are changed, two settling delays are implemented toallows the

SVS Operation6-6Supply Voltage Supervisor6.2.4 SVS Operating RangeEach SVS level has hysteresis to reduce sensitivity to small supply voltagechanges w

SVS Registers6-7Supply Voltage Supervisor6.3 SVS RegistersThe SVS registers are listed in Table 6−1.Table 6−1.SVS RegistersRegister Short Form Registe

Address Space1-4Introduction1.4 Address SpaceThe MSP430 von-Neumann architecture has one address space shared withspecial function registers (SFRs), p

6-8Supply Voltage Supervisor

7-1Hardware Multiplier &'""This chapter describes the hardware multiplier. The hardware multiplier isimplemented in

Hardware Multiplier Introduction7-2Hardware Multiplier7.1 Hardware Multiplier IntroductionThe hardware multiplier is a peripheral and is not part of t

Hardware Multiplier Operation7-3Hardware Multiplier7.2 Hardware Multiplier OperationThe hardware multiplier supports unsigned multiply, signed multipl

Hardware Multiplier Operation7-4Hardware Multiplier7.2.2 Result RegistersThe result low register RESLO holds the lower 16-bits of the calculation resu

Hardware Multiplier Operation7-5Hardware Multiplier7.2.3 Software ExamplesExamples for all multiplier modes follow. All 8x8 modes use the absoluteaddr

Hardware Multiplier Operation7-6Hardware Multiplier7.2.4 Indirect Addressing of RESLOWhen using indirect or indirect autoincrement addressing mode to

Hardware Multiplier Registers7-7Hardware Multiplier7.3 Hardware Multiplier RegistersThe hardware multiplier registers are listed in Table 7−4.Table 7−

7-8Hardware Multiplier

8-1 () ""The DMA controller module transfers data from one address to anotherwithout CPU intervention. This chapter describes the

Address Space1-5Introduction1.4.3 Peripheral ModulesPeripheral modules are mapped into the address space. The address spacefrom 0100 to 01FFh is reser

8-28.1 DMA IntroductionThe direct memory access (DMA) controller transfers data from one addressto another, without CPU intervention, across the entir

8-3Figure 8−1. DMA Controller Block DiagramDMA Priority And ControlENNMIDTDMA Channel 2DMASRSBYTEDMA2SZDMA2DADMA2SADMADSTBYTEDMASRCINCRxDMADSTINCRx223

8-48.2 DMA OperationThe DMA controller is configured with user software. The setup and operationof the DMA is discussed in the following sections.8.2.

8-58.2.2 DMA Transfer ModesThe DMA controller has six transfer modes selected by the DMADTx bits aslisted in Table 8−1. Each channel is individually c

8-6Single TransferIn single transfer mode, each byte/word transfer requires a separate trigger.The single transfer state diagram is shown in Figure 8−

8-7Figure 8−3. DMA Single Transfer State DiagramResetWait for TriggerIdleHold CPU,Transfer one word/byte[+Trigger AND DMALEVEL = 0 ]OR[Trigger=1 AND

8-8Block TransfersIn block transfer mode, a transfer of a complete block of data occurs after onetrigger. When DMADTx = 1, the DMAEN bit is cleared af

8-9Figure 8−4. DMA Block Transfer State DiagramResetWait for TriggerIdleHold CPU,Transfer one word/byte[+Trigger AND DMALEVEL = 0 ]OR[Trigger=1 AND D

8-10Burst-Block TransfersIn burst-block mode, transfers are block transfers with CPU activityinterleaved. The CPU executes 2 MCLK cycles after every f

8-11Figure 8−5. DMA Burst-Block Transfer State Diagram2 x MCLKResetWait for TriggerIdleHold CPU,Transfer one word/byteBurst State(release CPU for 2xMC

1-6Introduction

8-128.2.3 Initiating DMA TransfersEach DMA channel is independently configured for its trigger source with theDMAxTSELx bits as described in Table 8−2

8-13Table 8−2.DMA Trigger OperationDMAxTSELx Operation0000 A transfer is triggered when the DMAREQ bit is set. The DMAREQ bit is automatically resetwh

8-148.2.4 Stopping DMA TransfersThere are two ways to stop DMA transfers in progress:- A single, block, or burst-block transfer may be stopped with an

8-158.2.6 DMA Transfer Cycle TimeThe DMA controller requires one or two MCLK clock cycles to synchronizebefore each single transfer or complete block

8-168.2.7 Using DMA with System InterruptsDMA transfers are not interruptible by system interrupts. System interruptsremain pending until the completi

8-178.2.9 Using the I2C Module with the DMA ControllerThe I2C module provides two trigger sources for the DMA controller. The I2Cmodule can trigger a

8-188.3 DMA RegistersThe DMA registers are listed in Table 8−4:Table 8−4.DMA RegistersRegister Short Form Register Type Address Initial StateDMA contr

8-19DMACTL0, DMA Control Register 015 14 13 12 11 10 9 8Reserved DMA2TSELxrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)76543210DMA1TSELx DMA

8-20DMACTL1, DMA Control Register 115 14 13 12 11 10 9 80 0 0 0 0 0 0 0r0 r0 r0 r0 r0 r0 r0 r0765432100 0 0 0 0DMAONFETCHROUNDROBINENNMIr0 r0 r0 r0 r0

8-21DMAxCTL, DMA Channel x Control Register15 14 13 12 11 10 9 8Reserved DMADTx DMADSTINCRx DMASRCINCRxrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0

2-1System Resets, Interrupts, and Operating Modes This chapter describes the MSP430x1xx system resets, in

8-22DMASRCBYTEBit 6 DMA source byte. This bit selects the source as a byte or word.0 Word1 ByteDMALEVELBit 5 DMA level. This bit selects between edge-

8-23DMAxDA, DMA Destination Address Register15 14 13 12 11 10 9 8DMAxDAxrw rw rw rw rw rw rw rw76543210DMAxDAxrw rw rw rw rw rw rw rwDMAxDAx Bits15−0D

8-24

9-1Digital I/O ("*This chapter describes the operation of the digital I/O ports. Ports P1-P2 areimplemented in MSP430x11xx devices. Ports

Digital I/O Introduction9-2Digital I/O9.1 Digital I/O IntroductionMSP430 devices have up to 6 digital I/O ports implemented, P1 - P6. Each porthas eig

Digital I/O Operation9-3Digital I/O9.2 Digital I/O Operation The digital I/O is configured with user software. The setup and operation of thedigital I

Digital I/O Operation9-4Digital I/O9.2.4 Function Select Registers PxSELPort pins are often multiplexed with other peripheral module functions. See th

Digital I/O Operation9-5Digital I/O9.2.5 P1 and P2 InterruptsEach pin in ports P1 and P2 have interrupt capability, configured with thePxIFG, PxIE, an

Digital I/O Operation9-6Digital I/OInterrupt Edge Select Registers P1IES, P2IESEach PxIES bit selects the interrupt edge for the corresponding I/O pin

Digital I/O Registers9-7Digital I/O9.3 Digital I/O Registers Seven registers are used to configure P1 and P2. Four registers are used toconfigure port

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvemen

System Reset and Initialization2-2System Resets, Interrupts, and Operating Modes2.1 System Reset and InitializationThe system reset circuitry shown in

9-8Digital I/O

10-1Watchdog Timer + The watchdog timer is a 16-bit timer that can be used as a watchdog or as aninterval timer. This chapter describes t

Watchdog Timer Introduction10-2Watchdog Timer10.1 Watchdog Timer IntroductionThe primary function of the watchdog timer (WDT) module is to perform aco

Watchdog Timer Introduction10-3Watchdog TimerFigure 10−1. Watchdog Timer Block DiagramWDTQnY1234Q6Q9Q13Q1516−bitCounterCLKAB11AENPUCSMCLKACLKClearPass

Watchdog Timer Operation10-4Watchdog Timer10.2 Watchdog Timer OperationThe WDT module can be configured as either a watchdog or interval timer withthe

Watchdog Timer Operation10-5Watchdog Timer10.2.4 Watchdog Timer InterruptsThe WDT uses two bits in the SFRs for interrupt control.- The WDT interrupt

Watchdog Timer Operation10-6Watchdog Timer10.2.5 Operation in Low-Power ModesThe MSP430 devices have several low-power modes. Different clock signalsa

Watchdog Timer Registers10-7Watchdog Timer10.3 Watchdog Timer RegistersThe watchdog timer module registers are listed in Table 10−1.Table 10−1.Watchdo

Watchdog Timer Registers10-8Watchdog TimerWDTCTL, Watchdog Timer Register15 14 13 12 11 10 9 8Read as 069hWDTPW, must be written as 05Ah76543210WDTHOL

Watchdog Timer Registers10-9Watchdog TimerIE1, Interrupt Enable Register 176543210NMIIE WDTIErw−0 rw−0Bits7-5These bits may be used by other modules.

System Reset and Initialization2-3System Resets, Interrupts, and Operating Modes2.1.1 Power-On Reset (POR)When the VCC rise time is slow, the POR dete

Watchdog Timer Registers10-10Watchdog TimerIFG1, Interrupt Flag Register 176543210NMIIFG WDTIFGrw−(0) rw−(0)Bits7-5These bits may be used by other mod

11-1Timer_A ,)Timer_A is a 16-bit timer/counter with three capture/compare registers. Thischapter describes Timer_A. Timer_A is implemented in al

Timer_A Introduction11-2Timer_A11.1 Timer_A IntroductionTimer_A is a 16-bit timer/counter with three capture/compare registers.Timer_A can support mul

Timer_A Introduction11-3Timer_AFigure 11−1. Timer_A Block DiagramCompararator 2CCI15 0CCISxOUTMODxCaptureModeCMxSyncSCSCOVlogicOutputUnit2DSetQEQU0OUT

Timer_A Operation11-4Timer_A11.2 Timer_A OperationThe Timer_A module is configured with user software. The setup andoperation of Timer_A is discussed

Timer_A Operation11-5Timer_A11.2.2 Starting the TimerThe timer may be started, or restarted in the following ways:- The timer counts when MCx > 0 a

Timer_A Operation11-6Timer_AUp ModeThe up mode is used if the timer period must be different from 0FFFFh counts.The timer repeatedly counts up to the

Timer_A Operation11-7Timer_AContinuous ModeIn the continuous mode, the timer repeatedly counts up to 0FFFFh and restartsfrom zero as shown in Figure 1

Timer_A Operation11-8Timer_AUse of the Continuous ModeThe continuous mode can be used to generate independent time intervals andoutput frequencies. Ea

Timer_A Operation11-9Timer_AUp/Down ModeThe up/down mode is used if the timer period must be different from 0FFFFhcounts, and if symmetrical pulse gen

System Reset and Initialization2-4System Resets, Interrupts, and Operating Modes2.1.2 Brownout Reset (BOR)Some devices have a brownout reset circuit (

Timer_A Operation11-10Timer_AChanging the Period Register TACCR0When changing TACCR0 while the timer is running, and counting in the downdirection, th

Timer_A Operation11-11Timer_A11.2.4 Capture/Compare BlocksThree identical capture/compare blocks, TACCRx, are present in Timer_A.Any of the blocks may

Timer_A Operation11-12Timer_AFigure 11−11.Capture CycleSecondCaptureTakenCOV = 1CaptureTakenNoCaptureTakenReadTakenCaptureClear Bit COVin Register TAC

Timer_A Operation11-13Timer_A11.2.5 Output UnitEach capture/compare block contains an output unit. The output unit is usedto generate output signals s

Timer_A Operation11-14Timer_AOutput Example—Timer in Up ModeThe OUTx signal is changed when the timer counts up to the TACCRx value,and rolls from TAC

Timer_A Operation11-15Timer_AOutput Example—Timer in Continuous ModeThe OUTx signal is changed when the timer reaches the TACCRx andTACCR0 values, dep

Timer_A Operation11-16Timer_AOutput Example—Timer in Up/Down ModeThe OUTx signal changes when the timer equals TACCRx in either countdirection and whe

Timer_A Operation11-17Timer_A11.2.6 Timer_A InterruptsTwo interrupt vectors are associated with the 16-bit Timer_A module:- TACCR0 interrupt vector fo

Timer_A Operation11-18Timer_ATAIV Software ExampleThe following software example shows the recommended use of TAIV and thehandling overhead. The TAIV

Timer_A Registers11-19Timer_A11.3 Timer_A RegistersThe Timer_A registers are listed in Table 11−3:Table 11−3.Timer_A RegistersRegister Short Form Regi

System Reset and Initialization2-5System Resets, Interrupts, and Operating Modes2.1.3 Device Initial Conditions After System ResetAfter a POR, the ini

Timer_A Registers11-20Timer_ATACTL, Timer_A Control Register15 14 13 12 11 10 9 8Unused TASSELxrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)

Timer_A Registers11-21Timer_ATAR, Timer_A Register15 14 13 12 11 10 9 8TARxrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)76543210TARxrw−(0) r

Timer_A Registers11-22Timer_ATACCTLx, Capture/Compare Control Register15 14 13 12 11 10 9 8CMx CCISx SCS SCCI Unused CAPrw−(0) rw−(0) rw−(0) rw−(0) rw

Timer_A Registers11-23Timer_ACCIEBit 4 Capture/compare interrupt enable. This bit enables the interrupt request ofthe corresponding CCIFG flag.0 Inter

11-24Timer_A

12-1Timer_B ,Timer_B is a 16-bit timer/counter with multiple capture/compare registers. Thischapter describes Timer_B. Timer_B3 (three capture/c

Timer_B Introduction12-2Timer_B12.1 Timer_B IntroductionTimer_B is a 16-bit timer/counter with three or seven capture/compareregisters. Timer_B can su

Timer_B Introduction12-3Timer_BFigure 12−1. Timer_B Block DiagramCCR6Compararator 6CCI15 0OUTMODxCaptureModeCMxSyncCOVlogicOutputUnit6DSetQEQU0OUTOUT6

Timer_B Operation12-4Timer_B12.2 Timer_B OperationThe Timer_B module is configured with user software. The setup andoperation of Timer_B is discussed

Timer_B Operation12-5Timer_B12.2.2 Starting the TimerThe timer may be started or restarted in the following ways:- The timer counts when MCx > 0 an

System Reset and Initialization2-6System Resets, Interrupts, and Operating Modes2.2 InterruptsThe interrupt priorities are fixed and defined by the ar

Timer_B Operation12-6Timer_BUp ModeThe up mode is used if the timer period must be different from TBR(max) counts.The timer repeatedly counts up to th

Timer_B Operation12-7Timer_BContinuous ModeIn continuous mode the timer repeatedly counts up to TBR(max) and restartsfrom zero as shown in Figure 12−4

Timer_B Operation12-8Timer_BUse of the Continuous ModeThe continuous mode can be used to generate independent time intervals andoutput frequencies. Ea

Timer_B Operation12-9Timer_BUp/Down ModeThe up/down mode is used if the timer period must be different from TBR(max)counts, and if symmetrical pulse g

Timer_B Operation12-10Timer_BChanging the Value of Period Register TBCL0When changing TBCL0 while the timer is running, and counting in the downdirect

Timer_B Operation12-11Timer_B12.2.4 Capture/Compare BlocksThree or seven identical capture/compare blocks, TBCCRx, are present inTimer_B. Any of the b

Timer_B Operation12-12Timer_BFigure 12−11.Capture CycleSecondCaptureTakenCOV = 1CaptureTakenNoCaptureTakenReadTakenCaptureClear Bit COVin Register TBC

Timer_B Operation12-13Timer_BCompare Latch TBCLxThe TBCCRx compare latch, TBCLx, holds the data for the comparison to thetimer value in compare mode.

Timer_B Operation12-14Timer_B12.2.5 Output UnitEach capture/compare block contains an output unit. The output unit is usedto generate output signals s

Timer_B Operation12-15Timer_BOutput Example—Timer in Up ModeThe OUTx signal is changed when the timer counts up to the TBCLx value, androlls from TBCL

System Reset and Initialization2-7System Resets, Interrupts, and Operating Modes2.2.1 (Non)-Maskable Interrupts (NMI)(Non)-maskable NMI interrupts are

Timer_B Operation12-16Timer_BOutput Example—Timer in Continuous ModeThe OUTx signal is changed when the timer reaches the TBCLx and TBCL0values, depen

Timer_B Operation12-17Timer_BOutput Example − Timer in Up/Down ModeThe OUTx signal changes when the timer equals TBCLx in either countdirection and wh

Timer_B Operation12-18Timer_B12.2.6 Timer_B InterruptsTwo interrupt vectors are associated with the 16-bit Timer_B module:- TBCCR0 interrupt vector fo

Timer_B Operation12-19Timer_BTBIV, Interrupt Handler ExamplesThe following software example shows the recommended use of TBIV and thehandling overhead

Timer_B Registers12-20Timer_B12.3 Timer_B RegistersThe Timer_B registers are listed in Table 12−5:Table 12−5.Timer_B RegistersRegister Short Form Regi

Timer_B Registers12-21Timer_BTimer_B Control Register TBCTL15 14 13 12 11 10 9 8Unused TBCLGRPx CNTLx Unused TBSSELxrw−(0) rw−(0) rw−(0) rw−(0) rw−(0)

Timer_B Registers12-22Timer_BUnusedBit 3 UnusedTBCLRBit 2 Timer_B clear. Setting this bit resets TBR, the TBCLK divider, and the countdirection. The T

Timer_B Registers12-23Timer_BTBCCTLx, Capture/Compare Control Register15 14 13 12 11 10 9 8CMx CCISx SCS CLLDx CAPrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) r

Timer_B Registers12-24Timer_BCCIEBit 4 Capture/compare interrupt enable. This bit enables the interrupt request ofthe corresponding CCIFG flag.0 Inter

Timer_B Registers12-25Timer_BTBIV, Timer_B Interrupt Vector Register15 14 13 12 11 10 9 80 0 0 0 0 0 0 0r0 r0 r0 r0 r0 r0 r0 r0765432100 0 0 0 TBIVx 0

System Reset and Initialization2-8System Resets, Interrupts, and Operating ModesFigure 2−5. Block Diagram of (Non)-Maskable Interrupt SourcesFlash Mod

12-26Timer_B

13-1USART Peripheral Interface, UART Mode !) " - !)The universal synchronous/asynchronous receive/transmit (USART)

USART Introduction: UART Mode13-2USART Peripheral Interface, UART Mode13.1 USART Introduction: UART ModeIn asynchronous mode, the USART connects the M

USART Introduction: UART Mode13-3USART Peripheral Interface, UART ModeFigure 13−1. USART Block Diagram: UART ModeReceiver Shift RegisterTransmit Shift

USART Operation: UART Mode13-4USART Peripheral Interface, UART Mode13.2 USART Operation: UART ModeIn UART mode, the USART transmits and receives chara

USART Operation: UART Mode13-5USART Peripheral Interface, UART Mode13.2.3 Asynchronous Communication FormatsWhen two devices communicate asynchronousl

USART Operation: UART Mode13-6USART Peripheral Interface, UART ModeThe URXWIE bit is used to control data reception in the idle-linemultiprocessor for

USART Operation: UART Mode13-7USART Peripheral Interface, UART ModeAddress-Bit Multiprocessor FormatWhen MM = 1, the address-bit multiprocessor format

USART Operation: UART Mode13-8USART Peripheral Interface, UART ModeAutomatic Error DetectionGlitch suppression prevents the USART from being accidenta

USART Operation: UART Mode13-9USART Peripheral Interface, UART Mode13.2.4 USART Receive EnableThe receive enable bit, URXEx, enables or disables data

System Reset and Initialization2-9System Resets, Interrupts, and Operating ModesFlash Access ViolationThe flash ACCVIFG flag is set when a flash acces

USART Operation: UART Mode13-10USART Peripheral Interface, UART Mode13.2.5 USART Transmit EnableWhen UTXEx is set, the UART transmitter is enabled. Tr

USART Operation: UART Mode13-11USART Peripheral Interface, UART Mode13.2.6 UART Baud Rate GenerationThe USART baud rate generator is capable of produc

USART Operation: UART Mode13-12USART Peripheral Interface, UART ModeBaud Rate Bit TimingThe first stage of the baud rate generator is the 16-bit count

USART Operation: UART Mode13-13USART Peripheral Interface, UART ModeTransmit Bit TimingThe timing for each character is the sum of the individual bit

USART Operation: UART Mode13-14USART Peripheral Interface, UART ModeReceive Bit TimingReceive timing consists of two error sources. The first is the b

USART Operation: UART Mode13-15USART Peripheral Interface, UART ModeFor example, the receive errors for the following conditions are calculated:Baud r

USART Operation: UART Mode13-16USART Peripheral Interface, UART ModeTypical Baud Rates and ErrorsStandard baud rate frequency data for UxBRx and UxMCT

USART Operation: UART Mode13-17USART Peripheral Interface, UART Mode13.2.7 USART InterruptsThe USART has one interrupt vector for transmission and one

USART Operation: UART Mode13-18USART Peripheral Interface, UART ModeUSART Receive Interrupt OperationThe URXIFGx interrupt flag is set each time a cha

USART Operation: UART Mode13-19USART Peripheral Interface, UART ModeReceive-Start Edge Detect OperationThe URXSE bit enables the receive start-edge de

System Reset and Initialization2-10System Resets, Interrupts, and Operating ModesExample of an NMI Interrupt HandlerThe NMI interrupt is a multiple-so

USART Operation: UART Mode13-20USART Peripheral Interface, UART ModeReceive-Start Edge Detect ConditionsWhen URXSE = 1, glitch suppression prevents th

USART Registers: UART Mode13-21USART Peripheral Interface, UART Mode13.3 USART Registers: UART ModeTable 13−3 lists the registers for all devices impl

USART Registers: UART Mode13-22USART Peripheral Interface, UART ModeUxCTL, USART Control Register76543210PENA PEV SPB CHAR LISTEN SYNC MM SWRSTrw−0 rw

USART Registers: UART Mode13-23USART Peripheral Interface, UART ModeUxTCTL, USART Transmit Control Register76543210Unused CKPL SSELx URXSE TXWAKE Unus

USART Registers: UART Mode13-24USART Peripheral Interface, UART ModeUxRCTL, USART Receive Control Register76543210FE PE OE BRK URXEIE URXWIE RXWAKE RX

USART Registers: UART Mode13-25USART Peripheral Interface, UART ModeUxBR0, USART Baud Rate Control Register 0765432102726252423222120rw rw rw rw rw rw

USART Registers: UART Mode13-26USART Peripheral Interface, UART ModeUxRXBUF, USART Receive Buffer Register765432102726252423222120r r r r r r r rUxRXB

USART Registers: UART Mode13-27USART Peripheral Interface, UART ModeME1, Module Enable Register 176543210UTXE0†URXE0†rw−0 rw−0UTXE0†Bit 7 USART0 trans

USART Registers: UART Mode13-28USART Peripheral Interface, UART ModeIE1, Interrupt Enable Register 176543210UTXIE0†URXIE0†rw−0 rw−0UTXIE0†Bit 7 USART0

USART Registers: UART Mode13-29USART Peripheral Interface, UART ModeIFG1, Interrupt Flag Register 176543210UTXIFG0†URXIFG0†rw−1 rw−0UTXIFG0†Bit 7 USAR

System Reset and Initialization2-11System Resets, Interrupts, and Operating ModesEach individual peripheral interrupt is discussed in the associated p

USART Registers: UART Mode13-30USART Peripheral Interface, UART ModeUTXIFG0‡Bit 1 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty

13-31USART Peripheral Interface, UART Mode

14-1USART Peripheral Interface, SPI Mode !)"-The universal synchronous/asynchronous receive/transmit (USART)perip

USART Introduction: SPI Mode14-2USART Peripheral Interface, SPI Mode14.1 USART Introduction: SPI ModeIn synchronous mode, the USART connects the MSP43

USART Introduction: SPI Mode14-3USART Peripheral Interface, SPI ModeFigure 14−1. USART Block Diagram: SPI ModeReceiver Shift RegisterTransmit Shift Re

USART Operation: SPI Mode14-4USART Peripheral Interface, SPI Mode14.2 USART Operation: SPI ModeIn SPI mode, serial data is transmitted and received by

USART Operation: SPI Mode14-5USART Peripheral Interface, SPI Mode14.2.2 Master ModeFigure 14−2. USART Master and External SlaveReceive Buffer UxRXBUFR

USART Operation: SPI Mode14-6USART Peripheral Interface, SPI Mode14.2.3 Slave ModeFigure 14−3. USART Slave and External MasterReceive Buffer UxRXBUFRe

USART Operation: SPI Mode14-7USART Peripheral Interface, SPI Mode14.2.4 SPI EnableThe SPI transmit/receive enable bit USPIEx enables or disables the U

USART Operation: SPI Mode14-8USART Peripheral Interface, SPI ModeReceive EnableThe SPI receive enable state diagrams are shown in Figure 14−6 andFigur

Related Documentation From Texas Instrumentsiii PrefaceAbout This ManualThis manual discusses modules and peripherals of the MSP430x1x

System Reset and Initialization2-12System Resets, Interrupts, and Operating ModesReturn From InterruptThe interrupt handling routine terminates with t

USART Operation: SPI Mode14-9USART Peripheral Interface, SPI Mode14.2.5 Serial Clock ControlUCLK is provided by the master on the SPI bus. When MM = 1

USART Operation: SPI Mode14-10USART Peripheral Interface, SPI ModeSerial Clock Polarity and PhaseThe polarity and phase of UCLK are independently conf

USART Operation: SPI Mode14-11USART Peripheral Interface, SPI Mode14.2.6 SPI InterruptsThe USART has one interrupt vector for transmission and one int

USART Operation: SPI Mode14-12USART Peripheral Interface, SPI ModeSPI Receive Interrupt OperationThe URXIFGx interrupt flag is set each time a charact

USART Registers: SPI Mode14-13USART Peripheral Interface, SPI Mode14.3 USART Registers: SPI ModeThe USART registers, shown in Table 14−1 and Table 14−

USART Registers: SPI Mode14-14USART Peripheral Interface, SPI ModeUxCTL, USART Control Register76543210Unused Unused I2C†CHAR LISTEN SYNC MM SWRSTrw−0

USART Registers: SPI Mode14-15USART Peripheral Interface, SPI ModeUxTCTL, USART Transmit Control Register76543210CKPH CKPL SSELx Unused Unused STC TXE

USART Registers: SPI Mode14-16USART Peripheral Interface, SPI ModeUxRCTL, USART Receive Control Register76543210FE Unused OE Unused Unused Unused Unus

USART Registers: SPI Mode14-17USART Peripheral Interface, SPI ModeUxBR0, USART Baud Rate Control Register 0765432102726252423222120rw rw rw rw rw rw r

USART Registers: SPI Mode14-18USART Peripheral Interface, SPI ModeUxRXBUF, USART Receive Buffer Register765432102726252423222120r r r r r r r rUxRXBUF

System Reset and Initialization2-13System Resets, Interrupts, and Operating Modes2.2.4 Interrupt VectorsThe interrupt vectors and the power-up startin

USART Registers: SPI Mode14-19USART Peripheral Interface, SPI ModeME1, Module Enable Register 176543210USPIE0†rw−0Bit 7 This bit may be used by other

USART Registers: SPI Mode14-20USART Peripheral Interface, SPI ModeIE1, Interrupt Enable Register 176543210UTXIE0†URXIE0†rw−0 rw−0UTXIE0†Bit 7 USART0 t

USART Registers: SPI Mode14-21USART Peripheral Interface, SPI ModeUTXIE0‡Bit 1 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrup

USART Registers: SPI Mode14-22USART Peripheral Interface, SPI ModeIFG1, Interrupt Flag Register 176543210UTXIFG0†URXIFG0†rw−1 rw−0UTXIFG0†Bit 7 USART0

14-23USART Peripheral Interface, SPI Mode

15-1USART Peripheral Interface, I2C Mode !) " - . The universal synchronous/asynchronous receive/transmit (USART)p

I2C Module Introduction15-2USART Peripheral Interface, I2C Mode15.1 I2C Module IntroductionThe inter-IC control (I2C) module provides an interface bet

I2C Module Introduction15-3USART Peripheral Interface, I2C ModeFigure 15−1. USART Block Diagram: I2C ModeReceive Shift RegisterTransmit Shift Register

I2C Module Operation15-4USART Peripheral Interface, I2C Mode15.2 I2C Module OperationThe I2C module supports any slave or master I2C-compatible device

I2C Module Operation15-5USART Peripheral Interface, I2C Mode15.2.1 I2C Module InitializationThe I2C module is part of the USART peripheral. Individual

Operating Modes2-14System Resets, Interrupts, and Operating Modes2.3 Operating ModesThe MSP430 family is designed for ultralow-power applications and

I2C Module Operation15-6USART Peripheral Interface, I2C Mode15.2.2 I2C Serial DataOne clock pulse is generated by the master device for each data bitt

I2C Module Operation15-7USART Peripheral Interface, I2C Mode15.2.3 I2C Addressing ModesThe I2C module supports 7-bit and 10-bit addressing modes.7-Bit

I2C Module Operation15-8USART Peripheral Interface, I2C Mode15.2.4 I2C Module Operating ModesThe I2C module operates in master transmitter, master rec

I2C Module Operation15-9USART Peripheral Interface, I2C ModeFigure 15−8. Master Transmitter ModeIDLEGenerate STARTI2CBUSY Is Set4 x I2CPSCI2CBB Is Set

I2C Module Operation15-10USART Peripheral Interface, I2C ModeFigure 15−9. Master Receiver ModeIDLEGenerate START4 x I2CPSCI2CBB Is SetI2CSTT Is Cleare

I2C Module Operation15-11USART Peripheral Interface, I2C ModeArbitrationIf two or more master transmitters simultaneously start a transmission on theb

I2C Module Operation15-12USART Peripheral Interface, I2C ModeAutomatic Data Byte CountingAutomatic data byte counting is supported in master mode with

I2C Module Operation15-13USART Peripheral Interface, I2C ModeFigure 15−11.Slave TransmitterI2CBB Is ClearedSend DataLow ByteTo Master2nd StartDetected

I2C Module Operation15-14USART Peripheral Interface, I2C ModeFigure 15−12. Slave ReceiverIDLEI2CBB Is Cleared4 x I2CPSCYesReceive DataLow ByteFrom Mas

I2C Module Operation15-15USART Peripheral Interface, I2C Mode15.2.5 The I2C Data Register I2CDRThe I2CDR register can be accessed as an 8-bit or 16-bi

Operating Modes2-15System Resets, Interrupts, and Operating ModesFigure 2−10. MSP430x1xx Operating Modes For Basic Clock SystemActive ModeCPU Is Activ

I2C Module Operation15-16USART Peripheral Interface, I2C Mode15.2.6 I2C Clock Generation and SynchronizationThe I2C module is operated with the clock

I2C Module Operation15-17USART Peripheral Interface, I2C Mode15.2.7 Using the I2C Module with Low Power ModesThe I2C module can be used with MSP430 lo

I2C Module Operation15-18USART Peripheral Interface, I2C Mode15.2.8 I2C InterruptsThe I2C module has one interrupt vector for eight interrupt flags li

I2C Module Operation15-19USART Peripheral Interface, I2C ModeI2CIV, Interrupt Vector GeneratorThe I2C interrupt flags are prioritized and combined to

I2C Module Registers15-20USART Peripheral Interface, I2C Mode15.3 I2C Module RegistersThe I2C module registers are listed in Table 15−4.Table 15−4.I2C

I2C Module Registers15-21USART Peripheral Interface, I2C ModeU0CTL, USART0 Control Register-I2C Mode76543210RXDMAEN TXDMAEN I2C XA LISTEN SYNC MST I2C

I2C Module Registers15-22USART Peripheral Interface, I2C ModeI2CTCTL, I2C Transmit Control Register76543210I2CWORD I2CRM I2CSSELx I2CTRX I2CSTB I2CSTP

I2C Module Registers15-23USART Peripheral Interface, I2C ModeI2CDCTL, I2C Data Control Register76543210Unused Unused I2CBUSYI2CSCLLOWI2CSBD I2CTXUDF I

I2C Module Registers15-24USART Peripheral Interface, I2C ModeI2CDRW, I2CDRB, I2C Data Register15 14 13 12 11 10 9 8I2CDRW High Byterw−0 rw−0 rw−0 rw−0

I2C Module Registers15-25USART Peripheral Interface, I2C ModeI2CPSC, I2C Clock Prescaler Register76543210I2CPSCxrw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−

Operating Modes2-16System Resets, Interrupts, and Operating Modes2.3.1 Entering and Exiting Low-Power ModesAn enabled interrupt event wakes the MSP430

I2C Module Registers15-26USART Peripheral Interface, I2C ModeI2CSCLH, I2C Shift Clock High Register76543210I2CSCLHxrw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0

I2C Module Registers15-27USART Peripheral Interface, I2C ModeI2COA, I2C Own Address Register, 7-Bit Addressing Mode15 14 13 12 11 10 9 80 0 0 0 0 0 0

I2C Module Registers15-28USART Peripheral Interface, I2C ModeI2CSA, I2C Slave Address Register, 7-Bit Addressing Mode15 14 13 12 11 10 9 80 0 0 0 0 0

I2C Module Registers15-29USART Peripheral Interface, I2C ModeI2CIE, I2C Interrupt Enable Register76543210STTIE GCIE TXRDYIE RXRDYIE ARDYIE OAIE NACKIE

I2C Module Registers15-30USART Peripheral Interface, I2C ModeI2CIFG, I2C Interrupt Flag Register76543210STTIFG GCIFG TXRDYIFG RXRDYIFG ARDYIFG OAIFG N

I2C Module Registers15-31USART Peripheral Interface, I2C ModeI2CIV, I2C Interrupt Vector Register15 14 13 12 11 10 9 80 0 0 0 0 0 0 0r0 r0 r0 r0 r0 r0

15-32USART Peripheral Interface, I2C Mode

16-1Comparator_A ,)Comparator_A is an analog voltage comparator. This chapter describesComparator_A. Comparator_A is implemented in MSP430x1

Comparator_A Introduction16-2Comparator_A16.1 Comparator_A IntroductionThe comparator_A module supports precision slope analog-to-digitalconversions,

Comparator_A Introduction16-3Comparator_AFigure 16−1. Comparator_A Block DiagramCAOUT+−CAEX0.5x0.25xSet_CAIFGCA1CCI1B+−0VGDSP2CA0P2CA1CAFCARSELCAONCAR

Principles for Low-Power Applications2-17System Resets, Interrupts, and Operating Modes2.4 Principles for Low-Power ApplicationsOften, the most import

Comparator_A Operation16-4Comparator_A16.2 Comparator_A Operation The comparator_A module is configured with user software. The setup andoperation of

Comparator_A Operation16-5Comparator_A16.2.3 Output FilterThe output of the comparator can be used with or without internal filtering.When control bit

Comparator_A Operation16-6Comparator_A16.2.5 Comparator_A, Port Disable Register CAPDThe comparator input and output functions are multiplexed with th

Comparator_A Operation16-7Comparator_A16.2.7 Comparator_A Used to Measure Resistive ElementsThe Comparator_A can be optimized to precisely measure res

Comparator_A Operation16-8Comparator_AThe thermistor measurement is based on a ratiometric conversion principle.The ratio of two capacitor discharge t

Comparator_A Registers16-9Comparator_A16.3 Comparator_A RegistersThe Comparator_A registers are listed in Table 16−1:Table 16−1.Comparator_A Registers

Comparator_A Registers16-10Comparator_ACACTL1, Comparator_A Control Register 176543210CAEX CARSEL CAREFx CAON CAIES CAIE CAIFGrw−(0) rw−(0) rw−(0) rw−

Comparator_A Registers16-11Comparator_ACACTL2, Comparator_A, Control Register76543210Unused P2CA1 P2CA0 CAF CAOUTrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw

16-12Comparator_A

17-1ADC12 )(.The ADC12 module is a high-performance 12-bit analog-to-digital converter.This chapter describes the ADC12. The ADC12 is implemented in

2-18System Resets, Interrupts, and Operating Modes

ADC12 Introduction17-2ADC1217.1 ADC12 IntroductionThe ADC12 module supports fast, 12-bit analog-to-digital conversions. Themodule implements a 12-bit

ADC12 Introduction17-3ADC12Figure 17−1. ADC12 Block DiagramSampleandHoldVeREF+12−bit SARVR−−16 x 12MemoryBuffer−−16 x 8MemoryControl−VR+VREF+VeREF−VRE

ADC12 Operation17-4ADC1217.2 ADC12 OperationThe ADC12 module is configured with user software. The setup and operationof the ADC12 is discussed in the

ADC12 Operation17-5ADC1217.2.2 ADC12 Inputs and MultiplexerThe eight external and four internal analog signals are selected as the channelfor conversi

ADC12 Operation17-6ADC1217.2.3 Voltage Reference GeneratorThe ADC12 module contains a built-in voltage reference with two selectablevoltage levels, 1.

ADC12 Operation17-7ADC1217.2.5 Sample and Conversion TimingAn analog-to-digital conversion is initiated with a rising edge of the sampleinput signal S

ADC12 Operation17-8ADC12Pulse Sample ModeThe pulse sample mode is selected when SHP = 1. The SHI signal is used totrigger the sampling timer. The SHT0

ADC12 Operation17-9ADC12Sample Timing ConsiderationsWhen SAMPCON = 0 all Ax inputs are high impedance. When SAMPCON =1, the selected Ax input can be m

ADC12 Operation17-10ADC1217.2.6 Conversion MemoryThere are 16 ADC12MEMx conversion memory registers to store conversionresults. Each ADC12MEMx is conf

ADC12 Operation17-11ADC12Single-Channel Single-Conversion ModeA single channel is sampled and converted once. The ADC result is written tothe ADC12MEM

3-1RISC 16-Bit CPU   !This chapter describes the MSP430 CPU, addressing modes, and instructionset.Topic Page3.1 CPU Introduction 3-2. .

ADC12 Operation17-12ADC12Sequence-of-Channels ModeA sequence of channels is sampled and converted once. The ADC results arewritten to the conversion m

ADC12 Operation17-13ADC12Repeat-Single-Channel ModeA single channel is sampled and converted continuously. The ADC results arewritten to the ADC12MEMx

ADC12 Operation17-14ADC12Repeat-Sequence-of-Channels ModeA sequence of channels is sampled and converted repeatedly. The ADCresults are written to the

ADC12 Operation17-15ADC12Using the Multiple Sample and Convert (MSC) BitTo configure the converter to perform successive conversions automaticallyand

ADC12 Operation17-16ADC1217.2.8 Using the Integrated Temperature SensorTo use the on-chip temperature sensor, the user selects the analog inputchannel

ADC12 Operation17-17ADC1217.2.9 ADC12 Grounding and Noise ConsiderationsAs with any high-resolution ADC, appropriate printed-circuit-board layout andg

ADC12 Operation17-18ADC1217.2.10 ADC12 InterruptsThe ADC12 has 18 interrupt sources:- ADC12IFG0-ADC12IFG15- ADC12OV, ADC12MEMx overflow- ADC12TOV, ADC

ADC12 Operation17-19ADC12ADC12 Interrupt Handling Software ExampleThe following software example shows the recommended use of ADC12IVand the handling

ADC12 Registers17-20ADC1217.3 ADC12 RegistersThe ADC12 registers are listed in Table 17−2:Table 17−2.ADC12 RegistersRegister Short Form Register Type

ADC12 Registers17-21ADC12ADC12CTL0, ADC12 Control Register 015 14 13 12 11 10 9 8SHT1x SHT0xrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)765

CPU Introduction3-2RISC 16-Bit CPU3.1 CPU Introduction The CPU incorporates features specifically designed for modernprogramming techniques such as ca

ADC12 Registers17-22ADC12MSCBit 7 Multiple sample and conversion. Valid only for sequence or repeated modes.0 The sampling timer requires a rising edg

ADC12 Registers17-23ADC12ADC12CTL1, ADC12 Control Register 115 14 13 12 11 10 9 8CSTARTADDx SHSx SHP ISSHrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−

ADC12 Registers17-24ADC12ADC12SSELxBits4-3ADC12 clock source select00 ADC12OSC01 ACLK10 MCLK11 SMCLKCONSEQxBits2-1Conversion sequence mode select00 Si

ADC12 Registers17-25ADC12ADC12MCTLx, ADC12 Conversion Memory Control Registers76543210EOS SREFx INCHxrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)

ADC12 Registers17-26ADC12ADC12IE, ADC12 Interrupt Enable Register15 14 13 12 11 10 9 8ADC12IE15 ADC12IE14 ADC12IE13 ADC12IE12 ADC12IE11 ADC12IE10 ADC1

ADC12 Registers17-27ADC12ADC12IV, ADC12 Interrupt Vector Register15 14 13 12 11 10 9 80 0 0 0 0 0 0 0r0 r0 r0 r0 r0 r0 r0 r0765432100 0 ADC12IVx 0r0 r

17-28ADC12

18-1ADC10 )(/The ADC10 module is a high-performance 10-bit analog-to-digital converter.This chapter describes the ADC10. The ADC10 is implemented in

ADC10 Introduction18-2ADC1018.1 ADC10 IntroductionThe ADC10 module supports fast, 10-bit analog-to-digital conversions. Themodule implements a 10-bit

ADC10 Introduction18-3ADC10Figure 18−1. ADC10 Block Diagram100110000010000100110100010101100111SampleandHold10−bit SAR Divider/1 .. /8ACLKMCLKSMCLKADC

CPU Introduction3-3RISC 16-Bit CPUFigure 3−1. CPU Block Diagram015MDB − Memory Data Bus Memory Address Bus − MAB16Zero, ZCarry, COverflow, VNegative,

ADC10 Operation18-4ADC1018.2 ADC10 OperationThe ADC10 module is configured with user software. The setup and operationof the ADC10 is discussed in the

ADC10 Operation18-5ADC1018.2.2 ADC10 Inputs and MultiplexerThe eight external and four internal analog signals are selected as the channelfor conversi

ADC10 Operation18-6ADC1018.2.3 Voltage Reference GeneratorThe ADC10 module contains a built-in voltage reference with two selectablevoltage levels. Se

ADC10 Operation18-7ADC1018.2.5 Sample and Conversion TimingAn analog-to-digital conversion is initiated with a rising edge of sample inputsignal SHI.

ADC10 Operation18-8ADC10Sample Timing ConsiderationsWhen SAMPCON = 0 all Ax inputs are high impedance. When SAMPCON =1, the selected Ax input can be m

ADC10 Operation18-9ADC1018.2.6 Conversion ModesThe ADC10 has four operating modes selected by the CONSEQx bits asdiscussed in Table 18−1.Table 18−1.Co

ADC10 Operation18-10ADC10Single-Channel Single-Conversion ModeA single channel selected by INCHx is sampled and converted once. The ADCresult is writt

ADC10 Operation18-11ADC10Sequence-of-Channels ModeA sequence of channels is sampled and converted once. The sequencebegins with the channel selected b

ADC10 Operation18-12ADC10Repeat-Single-Channel ModeA single channel selected by INCHx is sampled and converted continuously.Each ADC result is written

ADC10 Operation18-13ADC10Repeat-Sequence-of-Channels ModeA sequence of channels is sampled and converted repeatedly. The sequencebegins with the chann

GlossaryivGlossaryACLK Auxiliary Clock See Basic Clock ModuleADC Analog-to-Digital ConverterBOR Brown-Out Reset See System Resets, Interrupts, and Ope

CPU Registers3-4RISC 16-Bit CPU3.2 CPU RegistersThe CPU incorporates sixteen 16-bit registers. R0, R1, R2 and R3 havededicated functions. R4 to R15 ar

ADC10 Operation18-14ADC10Using the MSC BitTo configure the converter to perform successive conversions automaticallyand as quickly as possible, a mult

ADC10 Operation18-15ADC1018.2.7 ADC10 Data Transfer ControllerThe ADC10 includes a data transfer controller (DTC) to automatically transferconversion

ADC10 Operation18-16ADC10One-Block Transfer ModeThe one-block mode is selected if the ADC10TB is reset. The value n inADC10DTC1 defines the total numb

ADC10 Operation18-17ADC10Figure 18−10. State Diagram for Data Transfer Control in One-Block Transfer ModeDTC idleDTC resetn=0 (ADC10DTC1)InitializeSta

ADC10 Operation18-18ADC10Two-Block Transfer ModeThe two-block mode is selected if the ADC10TB bit is set. The value n inADC10DTC1 defines the number o

ADC10 Operation18-19ADC10Figure 18−12. State Diagram for Data Transfer Control in Two-Block Transfer ModeDTC idleDTC resetADC10B1 = 0ADC10TB = 1n=0 (A

ADC10 Operation18-20ADC10Continuous TransferA continuous transfer is selected if ADC10CT bit is set. The DTC will not stopafter block one in (one-bloc

ADC10 Operation18-21ADC1018.2.8 Using the Integrated Temperature SensorTo use the on-chip temperature sensor, the user selects the analog inputchannel

ADC10 Operation18-22ADC1018.2.9 ADC10 Grounding and Noise ConsiderationsAs with any high-resolution ADC, appropriate printed-circuit-board layout andg

ADC10 Operation18-23ADC1018.2.10 ADC10 InterruptsOne interrupt and one interrupt vector are associated with the ADC10 asshown in Figure 18−17. When th

CPU Registers3-5RISC 16-Bit CPU3.2.2 Stack Pointer (SP)The stack pointer (SP/R1) is used by the CPU to store the return addressesof subroutine calls a

ADC10 Registers18-24ADC1018.3 ADC10 RegistersThe ADC10 registers are listed in Table 18−3.Table 18−3.ADC10 RegistersRegister Short Form Register Type

ADC10 Registers18-25ADC10ADC10CTL0, ADC10 Control Register 015 14 13 12 11 10 9 8SREFx ADC10SHTx ADC10SR REFOUT REFBURSTrw−(0) rw−(0) rw−(0) rw−(0) rw

ADC10 Registers18-26ADC10MSCBit 7 Multiple sample and conversion. Valid only for sequence or repeated modes.0 The sampling requires a rising edge of t

ADC10 Registers18-27ADC10ADC10CTL1, ADC10 Control Register 115 14 13 12 11 10 9 8INCHx SHSx ADC10DF ISSHrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(

ADC10 Registers18-28ADC10ADC10DIVxBits7-5ADC10 clock divider000 /1001 /2010 /3011 /4100 /5101 /6110 /7111 /8ADC10SSELxBits4-3ADC10 clock source select

ADC10 Registers18-29ADC10ADC10MEM, Conversion-Memory Register, Binary Format15 14 13 12 11 10 9 80 0 0 0 0 0 Conversion Resultsr0 r0 r0 r0 r0 r0 r r76

ADC10 Registers18-30ADC10ADC10DTC0, Data Transfer Control Register 076543210Reserved ADC10TB ADC10CT ADC10B1ADC10FETCHr0 r0 r0 r0 rw−(0) rw−(0) rw−(0)

ADC10 Registers18-31ADC10ADC10DTC1, Data Transfer Control Register 176543210DTC Transfersrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)DTCTra

18-32ADC10

19-1DAC12 ().The DAC12 module is a 12-bit, voltage output digital-to-analog converter. Thischapter describes the DAC12. Two DAC12 modules are implem

CPU Registers3-6RISC 16-Bit CPU3.2.3 Status Register (SR)The status register (SR/R2), used as a source or destination register, can beused in the regi

DAC12 Introduction19-2DAC1219.1 DAC12 IntroductionThe DAC12 module is a 12-bit, voltage output DAC. The DAC12 can beconfigured in 8- or 12-bit mode an

DAC12 Introduction19-3DAC12Figure 19−1. DAC12 Block DiagramDAC12_0DAC12_0OUT2.5V or 1.5V reference from ADC12DAC12SREFxVR−VR+DAC12_0DATDAC12_0LatchDAC

DAC12 Operation19-4DAC1219.2 DAC12 OperationThe DAC12 module is configured with user software. The setup and operationof the DAC12 is discussed in the

DAC12 Operation19-5DAC1219.2.2 DAC12 ReferenceThe reference for the DAC12 is configured to use either an external referencevoltage or the internal 1.5

DAC12 Operation19-6DAC1219.2.4 DAC12_xDAT Data FormatThe DAC12 supports both straight binary and 2’s compliment data formats.When using straight binar

DAC12 Operation19-7DAC1219.2.5 DAC12 Output Amplifier Offset CalibrationThe offset voltage of the DAC12 output amplifier can be positive or negative.W

DAC12 Operation19-8DAC1219.2.6 Grouping Multiple DAC12 ModulesMultiple DAC12s can be grouped together with the DAC12GRP bit tosynchronize the update o

DAC12 Operation19-9DAC1219.2.7 DAC12 InterruptsThe DAC12 interrupt vector is shared with the DMA controller. Software mustcheck the DAC12IFG and DMAIF

DAC12 Registers19-10DAC1219.3 DAC12 RegistersThe DAC12 registers are listed in Table 19−2:Table 19−2.DAC12 RegistersRegister Short Form Register Type

DAC12 Registers19-11DAC12DAC12_xCTL, DAC12 Control Register15 14 13 12 11 10 9 8Reserved DAC12SREFx DAC12RES DAC12LSELxDAC12CALONDAC12IRrw−(0) rw−(0)

CPU Registers3-7RISC 16-Bit CPU3.2.4 Constant Generator Registers CG1 and CG2Six commonly-used constants are generated with the constant generatorregi

DAC12 Registers19-12DAC12DAC12AMPxBits7-5DAC12 amplifier setting. These bits select settling time vs. currentconsumption for the DAC12 input and outpu

DAC12 Registers19-13DAC12DAC12_xDAT, DAC12 Data Register15 14 13 12 11 10 9 80 0 0 0 DAC12 Datar(0) r(0) r(0) r(0) rw−(0) rw−(0) rw−(0) rw−(0)76543210

19-14DAC12

CPU Registers3-8RISC 16-Bit CPU3.2.5 General−Purpose Registers R4 - R15The twelve registers, R4−R15, are general-purpose registers. All of theseregist

Addressing Modes3-9RISC 16-Bit CPU3.3 Addressing ModesSeven addressing modes for the source operand and four addressing modesfor the destination opera

Addressing Modes3-10RISC 16-Bit CPU3.3.1 Register ModeThe register mode is described in Table 3−4.Table 3−4.Register Mode DescriptionAssembler Code Co

Addressing Modes3-11RISC 16-Bit CPU3.3.2 Indexed ModeThe indexed mode is described in Table 3−5.Table 3−5.Indexed Mode DescriptionAssembler Code Conte

Addressing Modes3-12RISC 16-Bit CPU3.3.3 Symbolic ModeThe symbolic mode is described in Table 3−6.Table 3−6.Symbolic Mode DescriptionAssembler Code Co

Addressing Modes3-13RISC 16-Bit CPU3.3.4 Absolute ModeThe absolute mode is described in Table 3−7.Table 3−7.Absolute Mode DescriptionAssembler Code Co

Register Bit Conventionsv Register Bit ConventionsEach register is shown with a key indicating the accessibility of the eachindividual bit, and the

Addressing Modes3-14RISC 16-Bit CPU3.3.5 Indirect Register ModeThe indirect register mode is described in Table 3−8.Table 3−8.Indirect Mode Descriptio

Addressing Modes3-15RISC 16-Bit CPU3.3.6 Indirect Autoincrement ModeThe indirect autoincrement mode is described in Table 3−9.Table 3−9.Indirect Autoi

Addressing Modes3-16RISC 16-Bit CPU3.3.7 Immediate ModeThe immediate mode is described in Table 3−10.Table 3−10.Immediate Mode DescriptionAssembler Co

Instruction Set3-17RISC 16-Bit CPU3.4 Instruction SetThe complete MSP430 instruction set consists of 27 core instructions and 24emulated instructions.

Instruction Set3-18RISC 16-Bit CPU3.4.1 Double-Operand (Format I) InstructionsFigure 3−9 illustrates the double-operand instruction format.Figure 3−9.

Instruction Set3-19RISC 16-Bit CPU3.4.2 Single-Operand (Format II) InstructionsFigure 3−10 illustrates the single-operand instruction format.Figure 3−

Instruction Set3-20RISC 16-Bit CPU3.4.3 JumpsFigure 3−11 shows the conditional-jump instruction format.Figure 3−11. Jump Instruction FormatC 10-Bit PC

Instruction Set3-21 RISC 16−Bit CPUADC[.W] Add carry to destinationADC.B Add carry to destinationSyntax ADC dst or ADC.W dstADC.B dstOper

Instruction Set3-22 RISC 16−Bit CPUADD[.W] Add source to destinationADD.B Add source to destinationSyntax ADD src,dst or ADD.W src,dstADD.B src,dstOp

Instruction Set3-23 RISC 16−Bit CPUADDC[.W] Add source and carry to destinationADDC.B Add source and carry to destinationSyntax ADDC src,dst or ADDC.

vi

Instruction Set3-24 RISC 16−Bit CPUAND[.W] Source AND destinationAND.B Source AND destinationSyntax AND src,dst or AND.W src,dstAND.B src,dstOperation

Instruction Set3-25 RISC 16−Bit CPUBIC[.W] Clear bits in destinationBIC.B Clear bits in destinationSyntax BIC src,dst or BIC.W src,dstBIC.B src,dstOp

Instruction Set3-26 RISC 16−Bit CPUBIS[.W] Set bits in destinationBIS.B Set bits in destinationSyntax BIS src,dst or BIS.W src,dstBIS.B src,dstOperati

Instruction Set3-27 RISC 16−Bit CPUBIT[.W] Test bits in destinationBIT.B Test bits in destinationSyntax BIT src,dst or BIT.W src,dstOperation src .AN

Instruction Set3-28 RISC 16−Bit CPU* BR, BRANCH Branch to ... destinationSyntax BR dstOperation dst −> PCEmulation MOV dst,PCDescription An

Instruction Set3-29 RISC 16−Bit CPUCALL SubroutineSyntax CALL dstOperation dst −> tmp dst is evaluated and storedSP − 2 −> SPPC −> @S

Instruction Set3-30 RISC 16−Bit CPU* CLR[.W] Clear destination* CLR.B Clear destinationSyntax CLR dst or CLR.W dstCLR.B dstOperation 0 −> dstEmulat

Instruction Set3-31 RISC 16−Bit CPU* CLRC Clear carry bitSyntax CLRCOperation 0 −> CEmulation BIC #1,SRDescription The carry bit (C) is cleared.

Instruction Set3-32 RISC 16−Bit CPU* CLRN Clear negative bitSyntax CLRNOperation 0 → Nor(.NOT.src .AND. dst −> dst)Emulation BIC #4,SRDescription

Instruction Set3-33 RISC 16−Bit CPU* CLRZ Clear zero bitSyntax CLRZOperation 0 → Zor(.NOT.src .AND. dst −> dst)Emulation BIC #2,SRDescription The

Contentsvii 1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Instruction Set3-34 RISC 16−Bit CPUCMP[.W] Compare source and destinationCMP.B Compare source and destinationSyntax CMP src,dst or CMP.W src,dstCMP.

Instruction Set3-35 RISC 16−Bit CPU* DADC[.W] Add carry decimally to destination* DADC.B Add carry decimally to destinationSyntax DADC dst or D

Instruction Set3-36 RISC 16−Bit CPUDADD[.W] Source and carry added decimally to destinationDADD.B Source and carry added decimally to destinationSynt

Instruction Set3-37 RISC 16−Bit CPU* DEC[.W] Decrement destination* DEC.B Decrement destinationSyntax DEC dst or DEC.W dstDEC.B dstOperation dst −

Instruction Set3-38 RISC 16−Bit CPU* DECD[.W] Double-decrement destination* DECD.B Double-decrement destinationSyntax DECD dst or DECD.W ds

Instruction Set3-39 RISC 16−Bit CPU* DINT Disable (general) interruptsSyntax DINTOperation 0 → GIEor(0FFF7h .AND. SR → SR / .NOT.src .AND. dst −>

Instruction Set3-40 RISC 16−Bit CPU* EINT Enable (general) interruptsSyntax EINTOperation 1 → GIEor(0008h .OR. SR −> SR / .src .OR. dst −> dst

Instruction Set3-41 RISC 16−Bit CPU* INC[.W] Increment destination* INC.B Increment destinationSyntax INC dst or INC.W dstINC.B dstOperation dst + 1

Instruction Set3-42 RISC 16−Bit CPU* INCD[.W] Double-increment destination* INCD.B Double-increment destinationSyntax INCD dst or INCD.W dstINCD.B dst

Instruction Set3-43 RISC 16−Bit CPU* INV[.W] Invert destination* INV.B Invert destinationSyntax INV dstINV.B dstOperation .NOT.dst −> dstEmulation

Contentsviii3 RISC 16-Bit CPU 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Instruction Set3-44 RISC 16−Bit CPUJC Jump if carry setJHS Jump if higher or sameSyntax JC labelJHS labelOperation If C = 1: PC + 2 × offset −> PCI

Instruction Set3-45 RISC 16−Bit CPUJEQ, JZ Jump if equal, jump if zeroSyntax JEQ label, JZ labelOperation If Z = 1: PC + 2 × offset −> PCIf Z = 0

Instruction Set3-46 RISC 16−Bit CPUJGE Jump if greater or equalSyntax JGE labelOperation If (N .XOR. V) = 0 then jump to label: PC + 2 × offset −>

Instruction Set3-47 RISC 16−Bit CPUJL Jump if lessSyntax JL labelOperation If (N .XOR. V) = 1 then jump to label: PC + 2 × offset −> PCIf (N .XOR

Instruction Set3-48 RISC 16−Bit CPUJMP Jump unconditionallySyntax JMP labelOperation PC + 2 × offset −> PCDescription The 10-bit signed offset con

Instruction Set3-49 RISC 16−Bit CPUJN Jump if negativeSyntax JN labelOperation if N = 1: PC + 2 × offset −> PCif N = 0: execute following instruc

Instruction Set3-50 RISC 16−Bit CPUJNC Jump if carry not setJLO Jump if lowerSyntax JNC labelJLO labelOperation if C = 0: PC + 2 × offset −> PCif C

Instruction Set3-51 RISC 16−Bit CPUJNE Jump if not equalJNZ Jump if not zeroSyntax JNE labelJNZ labelOperation If Z = 0: PC + 2 × offset −> PCIf Z

Instruction Set3-52 RISC 16−Bit CPUMOV[.W] Move source to destinationMOV.B Move source to destinationSyntax MOV src,dst or MOV.W src,d

Instruction Set3-53 RISC 16−Bit CPU* NOP No operationSyntax NOPOperation NoneEmulation MOV #0, R3Description No operation is performed. The instruct

Contentsix 6 Supply Voltage Supervisor 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Instruction Set3-54 RISC 16−Bit CPU* POP[.W] Pop word from stack to destination* POP.B Pop byte from stack to destinationSyntax POP dstPOP.B dstOper

Instruction Set3-55 RISC 16−Bit CPUPUSH[.W] Push word onto stackPUSH.B Push byte onto stackSyntax PUSH src or PUSH.W srcPUSH.B srcOper

Instruction Set3-56 RISC 16−Bit CPU* RET Return from subroutineSyntax RETOperation @SP→ PCSP + 2 → SPEmulation MOV @SP+,PCDescription The return addre

Instruction Set3-57 RISC 16−Bit CPURETI Return from interruptSyntax RETIOperation TOS → SRSP + 2 → SPTOS → PCSP + 2 → SPDescription The status regis

Instruction Set3-58 RISC 16−Bit CPU* RLA[.W] Rotate left arithmetically* RLA.B Rotate left arithmeticallySyntax RLA dst or RLA.W dstRLA.B dstOperatio

Instruction Set3-59 RISC 16−Bit CPU* RLC[.W] Rotate left through carry* RLC.B Rotate left through carrySyntax RLC dst or RLC.W dstRLC.B dstOperation

Instruction Set3-60 RISC 16−Bit CPURRA[.W] Rotate right arithmeticallyRRA.B Rotate right arithmeticallySyntax RRA dst or RRA.W dstRRA.B dstOperation M

Instruction Set3-61 RISC 16−Bit CPURRC[.W] Rotate right through carryRRC.B Rotate right through carrySyntax RRC dst or RRC.W dstRRC dstOperation C −&

Instruction Set3-62 RISC 16−Bit CPU* SBC[.W] Subtract source and borrow/.NOT. carry from destination* SBC.B Subtract source and borrow/.NOT. carry fro

Instruction Set3-63 RISC 16−Bit CPU* SETC Set carry bitSyntax SETCOperation 1 −> CEmulation BIS #1,SRDescription The carry bit (C) is set.Status