Texas Instruments TMS320C2802 Manual do Utilizador

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015Digital Signal ProcessorsData ManualP

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

0.050.0100.0150.0200.0250.010 20 30 40 50 60 70 80 90 100SYSCLKOUT (MHz)Current (mA)IDD IDDA18 IDDIO IDD3VFL 3.3-V current1.8-V current0.0100.0200.03

Current Vs SYSCLKOUT02040608010012014016018020010 20 30 40 50 60 70 80 90 10SYSCLKOUT (MHz)Current (mA)IDD IDDA18 1.8v current IDDIO IDD3VFL 3.3v curr

EMU0EMU1TRSTTMSTDITDOTCKVDDIODSPEMU0EMU1TRSTTMSTDITDOTCKTCK_RET131421371196inchesorlessPDGNDGNDGNDGNDGND54681012JTAGHeaderVDDIOTMS320F2809, TMS320

Transmission Line4.0 pF 1.85 pFZ0 = 50 Ω(Α)Tester Pin ElectronicsData Sheet Timing Reference PointOutputUnderTest42 Ω 3.5 nHDevice Pin(B)TMS320F2809,

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

C4C3XCLKOUT(B)XCLKIN(A)C5C9C10C1C8C6TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015S

tw(RSL1)th(boot-mode)(B)VDDIO, VDD3VFLVDDA2, VDDAIO(3.3 V)XCLKINX1/X2XRSBoot-ModePinsVDD, VDD1A18,VDD2A18(1.8 V)XCLKOUTI/O Pins(C)User-Code DependentU

th(boot-mode)(A)tw(RSL2)XCLKINX1/X2XRSBoot-ModePinsXCLKOUTI/O PinsAddress/Data/Control(Internal)Boot-ROM Execution StartsUser-Code Execution StartsUse

OSCCLKSYSCLKOUTWrite to PLLCROSCCLK * 2(Current CPUFrequency)OSCCLK/2(CPU Frequency While PLL is StabilizingWith the Desired Frequency. This Period(PL

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

GPIO Signal1Sampling WindowOutput FromQualifier1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0 0SYSCLKOUTQUALPRD = 1(SYSCLKOUT/2)(SYSCLKOUT cycle * 2 * QUALPR

GPIOxnXCLKOUTtw(GPI)TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230

WAKE INT(A)XCLKOUTAddress/Data(internal)td(WAKE−IDLE)tw(WAKE−INT)TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801

tw(WAKE-INT)td(WAKE-STBY)td(IDLE−XCOL)Wake−upSignalX1/X2 orX1 or XCLKINXCLKOUTSTANDBY Normal ExecutionSTANDBYFlushing Pipeline(A)(B)(C)(D)(E)(F)Device

td(IDLE−XCOL)X1/X2 or XCLKINXCLKOUTHALT HALTWake-up LatencyFlushing Pipelinetd(WAKE−HALT)(A)(B)(C)(D)DeviceStatus(E)(G)(F)PLL Lock-up TimeNormalExecut

PWM(B)TZXCLKOUT(A)tw(TZ)td(TZ-PWM)HZTMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015w

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

ADCSOCAO orADCSOCBOtw(ADCSOCAL)XNMI, XINT1, XINT2tw(INT)Interrupt Vectortd(INT)Address bus (internal)TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802,

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

94SPISOMISPISIMOSPICLK (clock polarity = 1)SPICLK (clock polarity = 0)Master In DataMust Be ValidMaster Out Data Is Valid85321SPISTE(A)TMS320F2809, TM

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Data Valid11SPISOMISPISIMOSPICLK (clock polarity = 1)SPICLK (clock polarity = 0)Master In Data MustBe ValidMaster Out Data Is Valid1761032SPISTE(A)TMS

2015SPISIMOSPISOMISPICLK(clock polarity = 1)SPICLK(clock polarity = 0)SPISIMO DataMust Be ValidSPISOMI Data Is Valid1916141312SPISTE(A)TMS320F2809, TM

Data Valid22SPISIMOSPISOMISPICLK(clock polarity = 1)SPICLK(clock polarity = 0)SPISIMO DataMust Be ValidSPISOMI Data Is Valid211218171413SPISTE(A)TMS32

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

ADC Power Up DelayADC Ready for ConversionsPWDNBGPWDNREFPWDNADCRequest forADCConversiontd(BGR)td(PWD)TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802,

acRsADCIN0Cp10 pFRon1 kΩ1.64 pFChSwitchTypical Values of the Input Circuit Components:Switch Resistance (Ron): 1 kΩSampling Capacitor (Ch): 1.64 pFPa

Analog Input onChannel Ax or BxADC ClockSample and HoldSH PulseSMODE Bittdschx_ntdschx_n+1Sample nSample n+1Sample n+2tSHADC Event Trigger fromePWM or

Analog Input onChannel AxAnalog Input onChannel BxADC ClockSample and HoldSH PulsetSHtdschA0_ntdschB0_ntdschB0_n+1Sample nSample n+1Sample n+2tdschA0_

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

N +(SINAD * 1.76)6.02TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER

+ƪǒta(fp)tc(SCO)Ǔ* 1ƫ(round up to the next highest integer) or 0, whichever is larger(round up to the next highest integer) or 1, whichever is larger+

+ƪǒta(rp)tc(SCO)Ǔ* 1ƫ(round up to the next highest integer) or 0, whichever is larger+ƪǒta(rr)tc(SCO)Ǔ* 1ƫ(round up to the next highest integer) or 1,

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

PACKAGE OPTION ADDENDUMwww.ti.com5-Nov-2010Addendum-Page 1PACKAGING INFORMATIONOrderable DeviceStatus (1)Package Type PackageDrawingPins Package QtyEc

PACKAGE OPTION ADDENDUMwww.ti.com5-Nov-2010Addendum-Page 2Orderable DeviceStatus (1)Package Type PackageDrawingPins Package QtyEco Plan (2)Lead/Ball F

PACKAGE OPTION ADDENDUMwww.ti.com5-Nov-2010Addendum-Page 3Orderable DeviceStatus (1)Package Type PackageDrawingPins Package QtyEco Plan (2)Lead/Ball F

504948474645444342414039383736353433323130292827267677787980818283848586878889909192939495969798991007574737271706968676665646362616059585756555453525

PACKAGE OPTION ADDENDUMwww.ti.com5-Nov-2010Addendum-Page 4Orderable DeviceStatus (1)Package Type PackageDrawingPins Package QtyEco Plan (2)Lead/Ball F

MECHANICAL DATAMPBG028B FEBRUARY 1997 – REVISED MAY 20021POST OFFICE BOX 655303 • DALLAS, TEXAS 75265GGM (S–PBGA–N100) PLASTIC BALL GRID ARRAY 0,080,1

MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 19961POST OFFICE BOX 655303 • DALLAS, TEXAS 75265PZ (S-PQFP-G100) PLASTIC QUAD FLATP

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improveme

504948474645444342414039383736353433323130292827267677787980818283848586878889909192939495969798991007574737271706968676665646362616059585756555453525

504948474645444342414039383736353433323130292827267677787980818283848586878889909192939495969798991007574737271706968676665646362616059585756555453525

504948474645444342414039383736353433323130292827267677787980818283848586878889909192939495969798991007574737271706968676665646362616059585756555453525

4CBADE21 3KFGHJ5 76 98 10Bottom ViewTRSTTCKTDITDO TMSEMU0EMU1VDD3VFLTEST1TEST2XCLKOUTXCLKINX1X2XRSGPIO0GPIO1GPIO2 GPIO3 GPIO4GPIO5GPIO6GPIO7GPIO9 GPIO

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

INT[12:1]Real-Time JTAG(TDI, TDO, TRST, TCK,TMS, EMU0, EMU1)C28x CPU(100 MHz)NMI, INT13Memory BusINT14SYSCLKOUTRSCLKIN12-Bit ADCADCSOCA/BSOCA/B16 Chan

0x00 0000Block StartAddressData SpaceProg SpaceM0 Vector − RAM (32 x 32)(Enabled if VMAP = 0)M1 SARAM (1K y 16)0x00 0400Peripheral Frame 00x00 08000x0

0x00 0000Block StartAddressData SpaceProg SpaceM0 SARAM (1K y 16)M1 SARAM (1K y 16)0x00 0400Peripheral Frame 00x00 08000x00 0D00Peripheral Frame 1(pro

0x00 0000Block StartAddressData Space0x00 04000x00 08000x00 0D000x00 60000x00 70000x00 80000x00 90000x00 A0000x3D 78000x3D 7C000x3F 7FF80x3F 80000x3F

0x00 0000Block StartAddress0x00 04000x00 08000x00 0D000x00 60000x00 70000x00 80000x00 90000x3D 78000x3F 00000x3F 7FF80x3F 80000x3F 90000x3F F0000x3F F

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

0x00 0000Block StartAddress0x00 04000x00 08000x00 0D000x00 60000x00 70000x00 80000x00 90000x3D 78000x3F 40000x3F 7FF80x3F 80000x3F 90000x3F F0000x3F F

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

XINT2C28CPUCPUTIMER2(ReservedforDSP/BIOS)CPUTIMER0WatchdogPeripherals(SPI,SCI,I2C,eCAN,ePWM,eCAP,eQEP,ADC)TINT0InterruptControlXNMICR(15

INT12MUXINT11INT2INT1CPU(Enable)(Flag)INTxINTx.8PIEIERx(8:1) PIEIFRx(8:1)MUXINTx.7INTx.6INTx.5INTx.4INTx.3INTx.2INTx.1FromPeripherals orExternalInterr

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

PLLX1X2PowerModesControlWatchdogBlock28xCPUPeripheral BusLow-Speed PeripheralsSCI-A/B, SPI-A/B/C/DPeripheralRegistersHigh-Speed PrescalerLow-Speed Pre

X1XCLKIN (3.3-V clock input)On chiposcillatorX2xorPLLSTS[OSCOFF]OSCCLKPLLVCOCLK4-bit PLL Select (PLLCR)OSCCLK or VCOCLKCLKIN OSCCLK0PLLSTS[PLLOFF]nn ≠

External Clock Signal (Toggling 0−VDDIO)XCLKINX2NCX1External Clock Signal (Toggling 0−VDD)XCLKINX2NCX1CL1X2X1CrystalCL2XCLKINTMS320F2809, TMS320F2808,

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

/512OSCCLKWDCR (WDPS(2:0))WDCLKWDCNTR(7:0)WDKEY(7:0)Good Key1 0 1WDCR (WDCHK(2:0))BadWDCHKKeyWDCR (WDDIS)Clear CounterSCSR (WDENINT)WatchdogPrescalerG

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

BorrowResetTimer ReloadSYSCLKOUTTCR.4(Timer Start Status)TINT16-Bit Timer Divide-Down TDDRH:TDDR32-Bit Timer PeriodPRDH:PRD32-Bit CounterTIMH:TIM16-Bi

INT1toINT12INT14C28xTINT2TINT0PIECPU-TIMER0CPU-TIMER2(ReservedforDSP/BIOS)INT13TINT1CPU-TIMER1XINT13TMS320F2809, TMS320F2808, TMS320F2806TMS320F28

PIETZ1 to TZ6Peripheral BusePWM1 moduleePWM2 moduleePWMx moduleEPWM1SYNCIEPWM2SYNCIEPWM2SYNCOEPWMxSYNCIEPWMxSYNCOADCGPIOMUXEPWM1SYNCIEPWM1SYNCOADCSOCx

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

CTR = PRDTBPRD Shadow (16)TBPRD Active (16)CounterUp/Down(16-Bit)TBCNTActive (16)TBCTL[PHSEN]TBCTL[SWFSYNC](Software-Forced Sync)EPWMxSYNCICTR = ZEROC

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TSCTR(counter−32 bit)RSTCAP1(APRD active)LDCAP2(ACMP active)LDCAP3(APRD shadow)LDCAP4(ACMP shadow)LDContinuous /OneshotCapture ControlLD1LD2LD3LD4323

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

QWDTMRQWDPRD16QWDOGUTIMEQUPRDQUTMR32UTOUTWDTOUTQuadraturecapture unit(QCAP)QCPRDLATQCTMRLAT16QFLGQEPSTSQEPCTLRegistersused bymultiple unitsQCLKQDIRQIQ

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Digital Value + 0,Digital Value + 4096 Input Analog Voltage * ADCLO3when input ≤ 0 Vwhen 0 V < input < 3 Vwhen input ≥ 3 VDigital Value + 4095,

Result RegistersEPWMSOCBS/WGPIO/XINT2_ADCSOCEPWMSOCAS/WSequencer 2Sequencer 1SOCSOCADC Control Registers70B7h70B0h70AFh70A8hResult Reg 15Result Reg 8R

ADCINA[7:0]ADCINB[7:0]ADCLOADCREFINADC External Current Bias ResistorADCRESEXTADCREFPVDD1A18VDD2A18VSS1AGNDVSS2AGNDVDDAIOVSSAIOVDDA2VSSA2ADC Reference

ADCINA[7:0]ADCINB[7:0]ADCLOADCREFINADC External Current Bias Resistor ADCRESEXTADCREFPVDD1A18VDD2A18VSS1AGNDVSS2AGNDVDDAIOVSSAIOVDDA2VSSA2ADC Referenc

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Mailbox RAM(512 Bytes)32-Message Mailboxof 4 × 32-Bit WordsMemory ManagementUnitCPU Interface,Receive Control Unit,Timer Management UniteCAN Memory(51

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

Mailbox Enable − CANMEMailbox Direction − CANMDTransmission Request Set − CANTRSTransmission Request Reset − CANTRRTransmission Acknowledge − CANTAAbo

Mailbox Enable − CANMEMailbox Direction − CANMDTransmission Request Set − CANTRSTransmission Request Reset − CANTRRTransmission Acknowledge − CANTAAbo

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

Baud rate =LSPCLK16LSPCLK(BRR ) 1) * 8when BRR ≠ 0Baud rate = when BRR = 0Max bit rate +100 MHz16+ 6.25 106bńsMax bit rate +60 MHz16+ 3.75 106bńsT

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TX FIFO _0LSPCLKWUTFrame Format and ModeEven/Odd EnableParitySCI RX Interrupt select logicBRKDTRXRDYSCIRXST.6SCICTL1.38SCICTL2.1RX/BK INT ENASCIRXDSCI

Baud rate =LSPCLK4LSPCLK(SPIBRR ) 1)when SPIBRR = 3 to 127Baud rate = when SPIBRR = 0,1, 2TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F280

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

SSPICTL.0SPI INT FLAGSPI INTENASPISTS.6SClockPolarityTalkLSPCLK456 123 00123SPI Bit RateState ControlSPIRXBUFBuffer RegisterClockPhaseReceiverOverrun

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

SYSRSData[16]SYSCLKOUTData[16]Addr[16]ControlI2CINT1AI2CINT2AC28X CPUGPIOMUXI2C−ASystem ControlBlockI2CAENCLKPIEBlockSDAASCLAPeripheral BusTMS320F2809

GPxDAT (read)InputQualificationGPxMUX1/2High ImpedanceOutput ControlGPIOx pinXRS0 = Input, 1 = OutputLow PowerModes BlockGPxDIR (latch)Peripheral 2 In

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

GPyCTRL RegSYNCSYSCLKOUTQualificationInput Signal Qualified By 3 or 6 SamplesGPIOxTime between samplesGPxQSELNumber of SamplesTMS320F2809, TMS320F2808

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

PREFIXTMS 320 F 28015 PZTMX = Experimental DeviceTMP = Prototype DeviceTMS = Qualified DeviceDEVICE FAMILY320 = TMS320E DSP FamilyTECHNOLOGYPACKAGE TY

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015SPRS230L–OCTOBER 2003–REVISED DECEMBE

TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802TMS320C2801, TMS320F28016, TMS320F28015www.ti.comSPRS230L–OCTOBER 2003–REVIS