Texas Instruments TMS320C2802 Manual do Utilizador Página 118
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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230L–OCTOBER 2003–REVISED DECEMBER 2009
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6.10.4 I2C Electrical Specification and Timing
Table 6-33. I2C Timing
TEST CONDITIONS MIN MAX UNIT
f
SCL
SCL clock frequency I2C clock module frequency is between 400 kHz
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
V
il
Low level input voltage 0.3 V
DDIO
V
V
ih
High level input voltage 0.7 V
DDIO
V
V
hys
Input hysteresis 0.05 V
DDIO
V
V
ol
Low level output voltage 3 mA sink current 0 0.4 V
t
LOW
Low period of SCL clock I2C clock module frequency is between 1.3 μs
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
t
HIGH
High period of SCL clock I2C clock module frequency is between 0.6 μs
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
l
I
Input current with an input voltage –10 10 μA
between 0.1 V
DDIO
and 0.9 V
DDIO
MAX
6.10.5 Serial Peripheral Interface (SPI) Master Mode Timing
Table 6-34 lists the master mode timing (clock phase = 0) and Table 6-35 lists the timing (clock
phase = 1). Figure 6-20 and Figure 6-21 show the timing waveforms.
118 Electrical Specifications Copyright © 2003–2009, Texas Instruments Incorporated
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Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015
- Data Manual 1
- Contents 2
- Contents 3 3
- List of Figures 5
- List of Tables 7
- Digital Signal Processors 9
- 1.2 Getting Started 10
- 2 Introduction 11
- 2.1 Pin Assignments 14
- Introduction 15 15
- Introduction 17 17
- 2.2 Signal Descriptions 19
- See Table 2-2 for details 24
- 3 Functional Overview 25
- 3.1 Memory Maps 26
- Figure 3-3. F2808 Memory Map 27
- Figure 3-4. F2806 Memory Map 28
- Table 3-6. Wait-states 33
- 3.2 Brief Descriptions 34
- 3.2.1 C28x CPU 34
- 3.2.3 Peripheral Bus 34
- 3.2.5 Flash 35
- 3.2.6 ROM 35
- 3.2.7 M0, M1 SARAMs 35
- 3.2.8 L0, L1, H0 SARAMs 36
- 3.2.9 Boot ROM 36
- 3.2.10 Security 37
- 3.2.20 Control Peripherals 39
- 3.3 Register Map 40
- 3.5 Interrupts 42
- Functional Overview 43 43
- 3.5.1 External Interrupts 45
- 3.6 System Control 46
- 3.6.1 OSC and PLL Block 47
- PLLSTS[PLLLOCKS] = 1 49
- 3.6.2 Watchdog Block 51
- 3.7 Low-Power Modes Block 52
- 4 Peripherals 53
- Peripherals 57 57
- 4.3 Hi-Resolution PWM (HRPWM) 58
- Peripherals 59 59
- Value Register 60
- Peripherals 63 63
- 4.6.2 ADC Registers 67
- Table 4-7. CAN Register Map 72
- Peripherals 73 73
- Peripherals 75 75
- Table 4-13 77
- Table 4-10. SPI-A Registers 77
- Table 4-11. SPI-B Registers 77
- Table 4-12. SPI-C Registers 78
- Table 4-13. SPI-D Registers 78
- Peripherals 79 79
- Table 4-14. I2C-A Registers 81
- 4.11 GPIO MUX 82
- Table 4-15. GPIO Registers 83
- 5 Device Support 86
- 5.2 Documentation Support 88
- Device Support 89 89
- Device Support 91 91
- 6 Electrical Specifications 93
- 6.4 Current Consumption 95
- SYSCLKOUT 97
- 100-MHz SYSCLKOUT 98
- Device Power Vs SYSCLKOUT 101
- Submit Documentation Feedback 102
- 6.6.2 Test Load Circuit 103
- 6.6.3 Device Clock Table 104
- 6.8 Power Sequencing 106
- Figure 6-8. Power-on Reset 107
- Figure 6-9. Warm Reset 108
- 6.9.1 GPIO - Output Timing 109
- 6.9.2 GPIO - Input Timing 110
- XINT2_ADCSOC signal as well 111
- 6.10.2 Trip-Zone Input Timing 115
- Table 6-33. I2C Timing 118
- (1) (2) (3) (4) (5) 119
- 6.10.6 SPI Slave Mode Timing 123
- (1) (2) (3) (4) 124
- variation ±4 LSB 125
- SINAD * 1.76 130
- 6.12 Flash Timing 131
- 6.13 ROM Timing (C280x only) 132
- 7.1 Migration Issues 133
- 8 Revision History 134
- 9 Mechanical Data 135
- PACKAGE OPTION ADDENDUM 137
- MECHANICAL DATA 141
- MECHANICAL DATA 143
- IMPORTANT NOTICE 144
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