Texas Instruments TMS320C64X Manual do Utilizador descarregar pdf (Página 77)

DSP_fir_r8

4-49 C64x+ DSPLIB Reference

Implementation Notes

- Bank Conflicts: No bank conflicts occur.

- Interruptibility: The code is interruptible.

- The load double-word instruction is used to simultaneously load four

values in a single clock cycle.

- The inner loop is unrolled 4 times and will always compute a multiple of

4 output samples.

- The outer loop is conditionally executed in parallel with the inner loop. This

allows for a zero overhead outer loop.

Benchmarks Cycles nh*nr/4 + 17

Codesize 336 bytes

1 2 ... 72 73 74 75 76 77 78 79 80 81 82 ... 168 169

TMS320C64x+ DSP 1
Little-Endian DSP Library 1
Programmer’s Reference 1
Read This First 3
Trademarks 4
Contents 5
Introduction 9
1.2 Features and Benefits 12
Installing and Using DSPLIB 13
2.1 How to Install DSPLIB 14
2.2 Using DSPLIB 15
(log2(nx)−cei[log4(nx)−1]) 16
(log2(nx)) 16
2.3 How to Rebuild DSPLIB 17
DSPLIB Function Tables 19
3.2 DSPLIB Functions 21
3.3 DSPLIB Function Tables 22
Table 3−4. FFT (Continued) 23
Table 3−6. Math 24
Table 3−7. Matrix 24
Table 3−8. Miscellaneous 25
Table 3−9. Obsolete Functions 25
DSPLIB Reference 29
4.1 Adaptive Filtering 30
DSP_firlms2 31
4.2 Correlation 32
DSP_autocor 33
DSP_autocor_rA8 34
AutoCorrelation 34
DSP_fft16x16 36
DSP_fft16x16_imre 39
DSP_fft16x16r 42
DSP_fft16x32 52
DSP_fft32x32 54
DSP_fft32x32s 56
DSP_ifft16x16 58
DSP_ifft16x16_imre 60
DSP_ifft16x32 62
DSP_ifft32x32 64
4.4 Filtering and Convolution 66
DSP_fir_cplx 67
DSP_fir_cplx_hM4X4 68
Complex FIR Filter 68
DSP_fir_gen 70
FIR Filter 70
DSP_fir_gen_hM17_rA8X8 72
DSP_fir_r4 74
DSP_fir_r8 76
DSP_fir_r8_hM16_rM8A8X8 78
DSP_fir_sym 80
Symmetric FIR Filter 80
IIR With 5 Coefficients 82
DSP_iirlat 84
All-Pole IIR Lattice Filter 84
4.5 Math 86
DSP_dotp_sqr 87
DSP_dotprod 88
Vector Dot Product 88
DSP_maxval 90
Maximum Value of Vector 90
DSP_maxidx 91
DSP_minval 93
Minimum Value of Vector 93
DSP_mul32 94
32-Bit Vector Multiply 94
DSP_neg32 96
32-Bit Vector Negate 96
DSP_recip16 97
16-Bit Reciprocal 97
DSP_vecsumsq 99
Sum of Squares 99
DSP_w_vec 100
Weighted Vector Sum 100
4.6 Matrix 101
DSP_mat_mul 102
DSP_mat_trans 103
Matrix Transpose 103
4.7 Miscellaneous 104
DSP_bexp 105
DSP_blk_eswap16 106
DSP_blk_eswap32 108
DSP_blk_eswap64 110
DSP_blk_move 112
Block Move (Overlapping) 112
DSP_fltoq15 113
Float to Q15 Conversion 113
DSP_minerror 115
Minimum Energy Error Search 115
DSP_q15tofl 117
Q15 to Float Conversion 117
4.8 Obsolete Functions 118
DSP_bitrev_cplx 119
DSP_radix2 121
Complex Forward FFT (radix 2) 121
DSP_r4fft 123
Complex Forward FFT (radix 4) 123
DSP_fft16x16t 135
Appendix A 149
Performance Considerations 150
A.2 Fractional Q Formats 151
A.2.3 Q.31 Format 152
Appendix B 153
B.1 DSPLIB Software Updates 154
B.2 DSPLIB Customer Support 154
Glossary 155
C-3Glossary 157
C-5Glossary 159
C-7Glossary 161
C-9Glossary 163

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