Texas-instruments Digital Signal Processor SM320F2812-HT Manual do Utilizador descarregar pdf (Página 111)

Data Valid

SPISOMI

SPISIMO

SPICLK

(clock polarity = 1)

SPICLK

(clock polarity = 0)

Master In Data

Must Be Valid

Master Out Data Is Valid

SPISTE

(see Note A)

SM320F2812-HT

www.ti.com

SGUS062B– JUNE 2009– REVISED JUNE 2011

A. In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the

SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.

Figure 6-25. SPI Master External Timing (Clock Phase = 1)

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Texas-instruments Digital Signal Processor SM320F2812-HT Manual do Utilizador Página 111