Texas-instruments TMS320C6457 Manual do Utilizador

TMS320C6457 DSPHost Port Interface (HPI)User's GuideLiterature Number: SPRUGK7AMarch 2009–Revised July 2010

Introduction to the HPIwww.ti.comTable 2. HPI Signals (continued)Signal State(1)Host Connection DescriptionHCNTL[1:0] I Address or control pins The HP

www.ti.comUsing the Address Registers2 Using the Address RegistersThe HPI contains two 32-bit address registers: one for read operations (HPIAR) and o

Address or I/ORead/WriteChip selectData strobeAData/addressInterruptReadyHCNTL[1:0]HR/WHCSHDS1HDS2HD[31:0]HINTHRDYHPIHostAddress latch enable HASNo co

Address or I/ORead/WriteChip selectData strobeAData/addressInterruptReadyHCNTL[1:0]HR/WHCSHDS1HDS2HD[31:0]HINTHRDYHPIHostLogic high HASNo connect HHWI

Read/WriteChip selectData strobeADataInterruptReadyHCNTL[1:0]HR/WHCSHDS1HDS2HD[15:0]HINTHRDYHPIDSPHostHASHHWILLogic highLogic highAddressor I/OHD[31:1

HDS1HDS2HCSHRDYInternalHSTRBInternalHRDYwww.ti.comHPI OperationIf the host wants to read data from the DSP internal/external memory, the HPI DMA logic

HPI Operationwww.ti.com3.4 HCNTL[1:0] and HR/W: Indicating the Cycle TypeThe cycle type consists of:• The access type selected by the host by driving

www.ti.comHPI Operation3.5 HHWIL: Identifying the First and Second Halfwords in 16-Bit Multiplexed ModeIn the 16-bit multiplexed mode, each host cycle

Data 2Data 1HCSHASHSTRBHR/WHCNTL[1:0]HD[15:0]HRDYAHHWILInternalHPI latchescontrol informationHost latchesdataHPI latchescontrol informationHost latche

HCSHASHSTRBHR/WHCNTL[1:0]HRDYAHHWILData 1 Data 2HD[15:0]InternalHPI latchescontrol informationHPI latchesdataHPI latchescontrol informationHPI latches

2SPRUGK7A–March 2009–Revised July 2010Copyright © 2009–2010, Texas Instruments Incorporated

Data 2Data 1HCSHSTRBHR/WHCNTL[1:0]HD[15:0]HRDYAHHWILInternalHPI latchescontrol informationHost latchesdataHPI latchescontrol informationHost latchesda

HCSHSTRBHRDYAHR/WHCNTL[1:0]HHWILData 1 Data 2HD[15:0]InternalHPI latchescontrol informationHPI latchesdataHPI latchescontrol informationHPI latchesdat

Data 1HCSHSTRBHR/WHCNTL[1:0]HD[15:0]HRDYHHWILInternalValid00ValidHPI Operationwww.ti.com3.8 Single-Halfword HPIC Cycle in the 16-Bit Multiplexed ModeI

1st halfword00 or 10 00 or 102nd halfwordInternalHD[15:0]HRDYHHWILHR/WHCNTL[1:0]HCSHSTRBHCSHCNTL[1:0]HR/WHHWILInternalHSTRBHD[15:0]HRDY1st halfword 2n

1st halfword 2nd halfword0000InternalHD[15:0]HRDYHHWILHR/WHCNTL[1:0]HCSHSTRB10 10 11 111st halfword 2nd halfword2nd halfword1st halfwordInternalHSTRBH

10 10 01 01 011st halfword2nd halfword1st halfword2nd halfword1st halfwordInternalHSTRBHD[15:0]HRDYHHWILHR/WHCNTL[1:0]HCSHPIA write HPID+ writes00 or

1110HPIA Write HPID ReadHCNTL[1:0]HD[31:0]HRDYHR/WInternalHSTRBHCS10 01 01 01HPIA Write HPID+ ReadsHD[31:0]HRDYHCSAHCNTL[1:0]HR/WInternalHSTRBHPI Oper

00HCNTL[1:0]HD[31:0]HRDYHR/WInternalHSTRBHCS10 11HPIA Write HPID WriteHRDYHR/WInternalHSTRBHCSHCNTL[1:0]HD[31:0]www.ti.comHPI OperationFigure 22. HRDY

1001 0101HPIA Write HPID+ WritesHCNTL[1:0]HD[31:0]HRDYHR/WInternalHSTRBHCSA10010101HPIA Write HPID+ WritesHD[31:0]HRDYInternalHSTRBHCSAHCNTL[1:0]HR/WH

www.ti.comSoftware Handshaking Using the HPI Ready (HRDY) Bit4 Software Handshaking Using the HPI Ready (HRDY) BitIn addition to the HRDY output signa

Preface ... 61 Int

DSPINT=0DSPINT=1CPU writes 1to DSPINT bitInterruptpendingHost writes 0to DSPINT bitNo interrupt/interruptclearedHost writes 0 or 1to DSPINT bitCPU wri

HINT bit=0HINT signalis highis lowHINT signalHINT bit=1CPU writes 1to HINT bitHost writes 1to HINT bitInterruptactiveCPU writes 0to HINT bitNo interru

Write FIFOcontrol logicHost writepointerHPI DMAread pointerWrite FIFOHostwritesRead FIFOreadsHostcontrol logicRead FIFOHost readpointerHPI DMAwrite po

www.ti.comFIFOs and BurstingIf the host initiates an HPID read cycle with autoincrementing, the HPI DMA logic performs two 4-wordburst operations to f

FIFOs and Burstingwww.ti.com6.3 FIFO Flush ConditionsWhen specific conditions occur within the HPI, the read or write FIFO must be flushed to prevent

www.ti.comEmulation and Reset Considerations7 Emulation and Reset Considerations7.1 Emulation ModesThe FREE and SOFT bits of the power and emulation m

HPI Registerswww.ti.com8 HPI Registers8.1 IntroductionTable 6 lists the memory-mapped registers for the Host Port Interface (HPI). See the device-spec

www.ti.comHPI Registers8.2 Power and Emulation Management Register (PWREMU_MGMT)The power management and emulation register is shown in Figure 29 and

HPI Registerswww.ti.com8.3 Host Port Interface Control Register (HPIC)The HPIC register stores control and status bits used to configure and operate t

www.ti.comHPI RegistersTable 8. Host Port Interface Control Register (HPIC) Field Descriptions (continued)Bit Field Value Description9 DUALHPIA Dual-H

www.ti.comList of Figures1 HPI Position in the Host-DSP System ... 72

HPI Registerswww.ti.com8.4 Host Port Interface Address Registers (HPIAW and HPIAR)There are two 32-bit HPIA registers: HPIAW for write operations and

www.ti.comHPI Registers8.5 Data Register (HPID)The 32-bit register HPID provides the data path between the host and the HPI DMA logic. During a hostwr

www.ti.comAppendix A Revision HistoryThis revision history highlights the technical changes made to the document in this revision.Table 11. TMS320C645

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improveme

www.ti.comList of Tables1 Summary of HPI Registers ... 92

PrefaceSPRUGK7A–March 2009–Revised July 2010Read This FirstAbout This ManualThis guide describes the host port interface (HPI) on the TMS320C6457 digi

HPIDR/W FIFOsHPIAIncrementHPICAccesstypeHD[31:0]/HD[15:0]HDS1, HDS2HR/WHASHCNTL0HCNTL1(optional)HINTHRDYHPIHostDataAddressALER/WIRQReadyHCSChip select

Introduction to the HPIwww.ti.comThe HPI uses multiplexed operation, meaning the data bus carries both address and data. When the hostdrives an addres

www.ti.comIntroduction to the HPITable 1. Summary of HPI RegistersHost Access CPU AccessRead/Write Access Requirements Read/Write OffsetRegister Descr