Texas-instruments TMS320C6457 Manual do Utilizador descarregar pdf (Página 21)

HCS

HSTRB

HRDY

A

HR/W

HCNTL[1:0]

HHWIL

Data 1 Data 2

HD[15:0]

Internal

HPI latches

control information

HPI latches

data

HPI latches

control information

HPI latches

data

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HPI Operation

Figure 10. 16-Bit Multiplexed Mode Host Write Cycle With HAS Tied High

A Depending on the type of write operation (HPID without autoincrementing, HPIA, HPIC, or HPID with

autoincrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more information, see

Section 3.9.

21

SPRUGK7A–March 2009–Revised July 2010 Host Port Interface (HPI)

Copyright © 2009–2010, Texas Instruments Incorporated

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