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System Reset and Initialization
3-2
3.1 System Reset and Initialization
3.1.1 Introduction
The MSP430 system reset circuitry (shown in Figure 3–1) sources two internal
reset signals: power-on reset (POR) and power-up clear (PUC). Different
events trigger these reset signals and different initial conditions exist
depending on which signal was generated.
Figure 3–1. Power-On Reset and Power-Up Clear Schematic
V
CC
POR
Detect
V
CC
POR
Latch
S
S
R
POR
Latch
S
S
R
Resetwd1
Resetwd2
S
S
Delay
RST/MNI
NMI(WDTCTL.5)
†
TIMSEL
†
WDTQn
†
WDTIFG
†
EQU
†
MCLK
POR Delay
POR
PUC_DCO
PUC
†
From watchdog timer peripheral module
0 V0 V
0 V
KEYV
S
(from flash module)
A POR is a device reset. It is only generated by the two following events:
Powering up the device
A low signal on the RST/NMI pin when configured in the reset mode
A PUC is always generated when a POR is generated, but a POR is not
generated by a PUC. The following events trigger a PUC:
A POR signal
Watchdog timer expiration (in watchdog mode only)
Watchdog timer security key violation
A low signal on the RST/NMI pin when configured in the NMI mode
A Flash memory security key violation
Note:
If desired, software can cause a PUC by simply writing to the watchdog timer
control register with an incorrect password.
- User’s Guide 1
- Read This First 3
- Notational Conventions 4
- FCC Warning 4
- Contents 10
- Contents 11
- Contents 11
- Figures 13
- Figures 13
- Tables 19
- Examples 20
- Notes, Cautions, and Warnings 21
- 1.1 Features and Capabilities 24
- 1.2 11x Devices 25
- 1.3 11x1 Devices 25
- 1.4 13x Devices 26
- 1.5 14x Devices 26
- Architectural Overview 27
- 2.1 Introduction 28
- 2.2 Central Processing Unit 28
- 2.3 Program Memory 29
- 2.4 Data Memory 29
- 2.5 Operation Control 29
- 2.6 Peripherals 30
- System Resets, Interrupts 31
- 3.1.1 Introduction 32
- Rise Time 33
- Global Interrupt Structure 35
- 3.4 Interrupt Processing 39
- Interrupt Processing 40
- 3.4.2.1 External Interrupts 45
- 3.5 Operating Modes 46
- CPU is disabled 47
- MCLK is disabled 47
- SMCLK and ACLK remain active 47
- CPUOff = 1 49
- SCG0 = 1 49
- SCG1 = 0 49
- 3.5.3 Low-Power Mode 4 (LPM4) 51
- Potential Comment 52
- Chapter 4 53
- 4.1 Introduction 54
- 4.2 Data in the Memory 55
- 4.3 Internal ROM Organization 56
- Internal ROM Organization 57
- 4.4.1 Random Access Memory 58
- Figure 4–6. Register 59
- 4.4.2.1 Word Modules 60
- 4.4.2.2 Byte Modules 61
- 16-Bit CPU 65
- 5.1 CPU Registers 66
- Figure 5–3. Stack Usage 67
- CPU Registers 68
- 5.2 Addressing Modes 71
- 5.2.1 Register Mode 72
- 5.2.2 Indexed Mode 73
- 5.2.3 Symbolic Mode 74
- 5.2.4 Absolute Mode 75
- 5.2.5 Indirect Mode 76
- Addressing Modes 77
- 5.2.7 Immediate Mode 78
- 5.2.8.1 Format-I Instructions 79
- 5.3 Instruction Set Overview 81
- 5.3.3 Conditional Jumps 84
- 5.3.5 Miscellaneous 86
- 5.4 Instruction Map 87
- Hardware Multiplier 89
- 16-Bit Hardware Multiplier 91
- Hardware Multiplier Operation 92
- Hardware Multiplier Registers 97
- Basic Clock Module 101
- 7.1 Basic Clock Module 102
- 7.2 LFXT1 and XT2 Oscillators 104
- 7.2.2 XT2 Oscillator 105
- LFXT1 and XT2 Oscillators 106
- Figure 7–10. DCO Schematic 110
- System Resets, Interrupts and 114
- Operating Modes 114
- Mode for MCLK 117
- LFXT1CLK for Clock MCLK 117
- Digital I/O Configuration 121
- 8.1 Introduction 122
- 8.2 Ports P1, P2 123
- Table 8–1.Port P1 Registers 124
- Table 8–2.Port P2 Registers 124
- Ports P1, P2 125
- 8.3 Ports P3, P4, P5, P6 129
- 8.3.1.1 Input Registers 130
- 8.3.1.2 Output Registers 130
- 8.3.1.3 Direction Registers 130
- 8.3.2 Port P3–P6 Schematic 131
- Watchdog Timer 133
- 9.1 The Watchdog Timer 134
- Table 9–1.WDTCNT Taps 135
- Figure 9–3. Reading WDTCTL 136
- Figure 9–4. Writing to WDTCTL 136
- 9.1.3.1 Watchdog Mode 137
- 9.1.3.2 Timer Mode 138
- 9.1.3.4 Software Example 139
- Chapter 10 141
- 10.1 Introduction 142
- Introduction 143
- 10.2 Timer_A Operation 144
- Timer_A Operation 145
- 10.2.3 Starting the Timer 146
- 10.3 Timer Modes 147
- 10.3.2.1 Timer in Up Mode 148
- Figure 10–9. Timer 149
- Continuous Mode 149
- 10.3.4 Timer—Up/Down Mode 150
- Timer Modes 151
- Figure 10–16. Altering CCR0 152
- Timer in Up/Down Mode 152
- 10.4 Capture/Compare Blocks 153
- Figure 10–19. Capture Signal 155
- Figure 10–20. Capture Cycle 156
- Capture Initiated by Software 157
- 10.5 The Output Unit 159
- 10.5.2 Output Control Block 161
- 10.5.3 Output Examples 162
- 10.6 Timer_A Registers 164
- Table 10–4.Mode Control 165
- Figure 10–28. TAR Register 166
- Timer_A Registers 167
- 10.7 Timer_A UART 173
- Timer_A UART 174
- Chapter 11 177
- 11.1 Introduction 178
- 11.2 Timer_B Operation 181
- Table 11–1. Timer Modes 182
- 11.2.4 Starting the Timer 183
- 11.3 Timer Modes 184
- Immediate Mode for TBCL0 185
- 11.3.3 Timer—Continuous Mode 186
- 11.3.4 Timer—Up/Down Mode 188
- 11.4 Capture/Compare Blocks 191
- Figure 11–19.Capture Signal 192
- Figure 11–20.Capture Cycle 193
- 11.5 The Output Unit 199
- 11.5.2 Output Control Block 201
- 11.5.3 Output Examples 202
- 11.6 Timer_B Registers 205
- Table 11–5. Mode Control 206
- Timer_B Registers 207
- Figure 11–28.TBR Register 208
- 11.6.4.5 Timing Limits 216
- Chapter 12 217
- USART Peripheral Interface 218
- 12.3 Asynchronous Operation 220
- Asynchronous Operation 221
- Example 12–1. 4800 Baud 222
- Example 12–2. 19,200 Baud 222
- Figure 12–7. Idle 223
- Line Multiprocessor Format 223
- Figure 12–11.Address 226
- Bit Multiprocessor Format 226
- SPI Mode 231
- Control and Status Registers 232
- Figure 12–23. Receive 238
- Start Conditions 238
- Figure 12–24. Receive 239
- 12.7 Baud Rate Considerations 241
- Baud Rate Considerations 242
- 12.7.3 Synchronization Error 244
- Chapter 13 247
- 13.2.1 SPI Mode Features 249
- 13.3 Synchronous Operation 250
- Synchronous Operation 251
- 13.3.1 Master SPI Mode 253
- 13.3.2 Slave SPI Mode 254
- 13.5.1 USART Control Register 262
- Comparator_A 267
- 14.1 Comparator_A Overview 268
- 14.2 Comparator_A Description 269
- Comparator_A Description 270
- Comparator_A in Applications 275
- With Applied Analog Signals 276
- This example uses the 0.25×V 281
- Chapter 15 291
- 15.1 Introduction 292
- Sampling 293
- 15.2.1 ADC Core 294
- 15.2.2 Reference 295
- 15.3.1 Analog Multiplexer 296
- 15.4 Conversion Memory 298
- 15.5 Conversion Modes 299
- Conversion Modes 300
- 15.5.6 Power Down 310
- 12–bit S A R 312
- 15.7.3 Sampling Modes 314
- 15.7.3.2 Extended-Sample Mode 316
- 15.8 ADC12 Control Registers 320
- ADC12 Control Registers 321
- ADC12 Interrupt Vector 322
- Register ADC12IV 322
- ADC12IEN.x 327
- Note: Basic Clock System 330
- CPU clock MCLK 330
- Peripheral File Map 333
- A.1 Overview 334
- A.3 Digital I/O, Byte Access 335
- Only modifiable when ENC=0 342
- Watchdog/Timer, Word Access 343
- Instruction Set Description 351
- B.1 Instruction Set Overview 352
- Instruction Set Overview 353
- B.1.1 Instruction Formats 354
- B.1.3 Emulated Instructions 356
- Instruction Set Description 359
- Clear carry bit 369
- Clear negative bit 370
- Decrement destination 375
- Figure B–4.Decrement Overlap 376
- ] Increment destination 380
- Jump if greater or equal 385
- Jump if less 386
- Jump unconditionally 387
- Jump if negative 388
- No operation 392
- Rotate left arithmetically 397
- Rotate left through carry 398
- Flash Memory 413
- C.1 Flash Memory Organization 414
- Simultaneously 415
- Flash Memory Organization 416
- Figure C–4 417
- FUNCTION PERFORMED 420
- CLR &0F012h 421
- C.5.1 Flash Memory Protection 434
- Execution Outside this Module 435
- Outside This Flash Module 438
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