Texas-instruments TMS320C3x Manual do Utilizador descarregar pdf (Página 303)

External Memory Interface Timing

TMS320C30 and TMS320C31 External-Memory Interface

9.6.3 Hold Cycles

Figure 9–26 illustrates the timing for HOLD and HOLDA. HOLD is an external

asynchronous input. There is a minimum of one cycle delay from the time when

the processor recognizes HOLD

= 0 until HOLDA = 0. When HOLDA = 0, the

address, data buses, and associated strobes are placed in a high-impedance

state. All accesses occurring over an interface are completed before a hold is

acknowledged.

Figure 9–26. HOLD and HOLDA Timing

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