Texas-instruments TMS320C3x Manual do Utilizador descarregar pdf (Página 404)

100

101

Serial Ports

12-25

Peripherals

12.2.4 Receive/Transmit Timer-Control Register

A 32-bit receive/transmit timer-control register contains the control bits for the

timer module. At reset, all bits are set to 0. Figure 12–16 shows the register.

Bits 5–0 control the transmitter timer. Bits 11–6 control the receiver timer. The

serial port receive/transmit timer function is similar to timer module operation.

It can be considered a 16-bit-wide timer. Table 12–5 describes the register

bits, bit names, and bit functions.

Figure 12–16. Receive/Transmit Timer-Control Register

xx xx

XGOXHLD

XC/P

R/W

XCLKSRC

RSTAT

RCLKSRC

RC/P

RHLD

RGO

XSTAT

31 16 15 12 11 10 9 8 7 6 5 4 3 1

R/WRR/W R/WR/W R/W

R R/W

R/W

Notes: 1) R = read, W = write

2) xx = reserved bit, read as 0

Table 12–5. Receive/Transmit Timer-Control Register Register Bits Summary

Abbreviation

Reset

Value

Name Function

XGO 0 Transmit timer counter

restart

Resets and restarts the transmit timer counter.

If XGO = 1 and the timer is not held, the counter is zeroed

and begins incrementing on the next rising edge of the timer

input clock.

The XGO bit is cleared on the same rising edge. Writing 0

to XGO has no effect on the transmit timer.

XHLD 0 Transmit counter hold

signal

If XHLD = 0, the counter is disabled and held in its current

state.

If XHLD

= 1, the internal divide-by-two counter is also held so

that the counter continues where it left off.

XC/P

0 Transmit clock/pulse

mode control

When XC/P = 1, the clock mode is chosen. The signaling of

the status flag and external output has a 50 percent duty

cycle.

When XC/P

= 0, the status flag and external output are active

for one CLKOUT cycle during each timer period.

1 2 ... 399 400 401 402 403 404 405 406 407 408 409 ... 756 757

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