Texas-instruments TMS320C64x DSP Manual do Utilizador descarregar pdf (Página 25)

100

101

Video Port FIFO

Overview1-8 SPRU629

For Y/C video capture, the FIFO is configured as a single channel split into sep-

arate Y, Cb, and Cr buffers with separate write pointers and read registers

(YSRCA, CBSRCA, and CRSRCA). Figure 1–4 shows how Y data is received

on the VDIN[9–0] half of the bus and Cb/Cr data is received on the

VDIN[19–10] half of the bus and demultiplexed into the Cb and Cr buffers.

Figure 1–4. Y/C Video Capture FIFO Configuration

VDIN[19–10]

Cr Buffer (1280 bytes)

Cb Buffer (1280 bytes)

8/10

CRSRCA

CBSRCA

Y Buffer (2560 bytes)

VDIN[9–0]

8/10

Capture FIFO

YSRCA

1 2 ... 20 21 22 23 24 25 26 27 28 29 30 ... 305 306

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