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5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER)

EMAC Port Registers

The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in Figure 56 and

described in Table 56 .

Figure 56. Receive Channel n Free Buffer Count Register (RX nFREEBUFFER)

31 16

Reserved

R-0

15 0

RX nFREEBUF

WI-0

tLEGEND: R = Read only; R/W = Read/Write; WI = Write to increment; - n = value after reset

Table 56. Receive Channel n Free Buffer Count Register (RX nFREEBUFFER) Field Descriptions

Bit Field Value Description

31-16 Reserved 0 Reserved

15-0 RX nFREEBUF Receive free buffer count. These bits contain the count of free buffers available. The

RXFILTERTHRESH value is compared with this field to determine if low priority frames should be

filtered. The RX nFLOWTHRESH value is compared with this field to determine if receive flow

control should be issued against incoming packets (if enabled). This is a write-to-increment field.

This field rolls over to zero on overflow. If hardware flow control or QOS is used, the host must

initialize this field to the number of available buffers (one register per channel). The EMAC

decrements (by the number of buffers in the received frame) the associated channel register for

each received frame. The host must write this field with the number of buffers that have been freed

due to host processing.

Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)112 SPRU975B – August 2006

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